Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents Altera_PLL Parameter Values for External PLL Mode

The following example shows the clocking requirements to generate output clocks for ALTLVDS_TX and ALTLVDS_RX using the Altera_PLL IP core. The example sets the phase shift with the assumption that the clock and data are edge aligned at the pins of the device.

Note: For other clock and data phase relationships, Altera recommends that you first instantiate your ALTLVDS_RX and ALTLVDS_TX interface without using the external PLL mode option. Compile the IP cores in the Intel® Quartus® Prime software and take note of the frequency, phase shift, and duty cycle settings for each clock output. Enter these settings in the Altera_PLL IP core parameter editor and then connect the appropriate output to the ALTLVDS_RX and ALTLVDS_TX IP cores.
Table 38.  Example: Generating Output Clocks Using an Altera_PLL IP Core This table lists the parameter values that you can set in the Altera_PLL parameter editor to generate three output clocks using an Altera_PLL IP core if you are not using DPA and soft-CDR mode.


(Connects to the tx_inclock port of ALTLVDS_TX and the rx_inclock port of ALTLVDS_RX)


(Connects to the tx_enable port of ALTLVDS_TX and the rx_enable port of ALTLVDS_RX)


(Used as the core clock for the parallel data registers for both transmitter and receiver)


data rate

data rate/serialization factor

data rate/serialization factor

Phase shift


[(deserialization factor – 2)/deserialization factor] x 360°

–180/serialization factor

(outclk0 phase shift divided by the serialization factor)

Duty cycle


100/serialization factor


Figure 75. Phase Relationship for External PLL Interface Signals