Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

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ID 683375
Date 10/18/2023
Public
Document Table of Contents
Document Table of Contents x
1. Logic Array Blocks and Adaptive Logic Modules in Cyclone® V Devices 2. Embedded Memory Blocks in Cyclone® V Devices 3. Variable Precision DSP Blocks in Cyclone® V Devices 4. Clock Networks and PLLs in Cyclone® V Devices 5. I/O Features in Cyclone® V Devices 6. External Memory Interfaces in Cyclone® V Devices 7. Configuration, Design Security, and Remote System Upgrades in Cyclone® V Devices 8. SEU Mitigation for Cyclone® V Devices 9. JTAG Boundary-Scan Testing in Cyclone® V Devices 10. Power Management in Cyclone® V Devices
1. Logic Array Blocks and Adaptive Logic Modules in Cyclone® V Devices x
1.1. LAB 1.2. ALM Operating Modes 1.3. Logic Array Blocks and Adaptive Logic Modules in Cyclone® V Devices Revision History
1.1. LAB x
1.1.1. MLAB 1.1.2. Local and Direct Link Interconnects 1.1.3. LAB Control Signals 1.1.4. ALM Resources 1.1.5. ALM Output
1.2. ALM Operating Modes x
1.2.1. Normal Mode 1.2.2. Extended LUT Mode 1.2.3. Arithmetic Mode 1.2.4. Shared Arithmetic Mode
2. Embedded Memory Blocks in Cyclone® V Devices x
2.1. Types of Embedded Memory 2.2. Embedded Memory Design Guidelines for Cyclone® V Devices 2.3. Embedded Memory Features 2.4. Embedded Memory Modes 2.5. Embedded Memory Clocking Modes 2.6. Parity Bit in Memory Blocks 2.7. Byte Enable in Embedded Memory Blocks 2.8. Memory Blocks Packed Mode Support 2.9. Memory Blocks Address Clock Enable Support 2.10. Embedded Memory Blocks in Cyclone® V Devices Revision History
2.1. Types of Embedded Memory x
2.1.1. Embedded Memory Capacity in Cyclone V Devices
2.2. Embedded Memory Design Guidelines for Cyclone® V Devices x
2.2.1. Guideline: Consider the Memory Block Selection 2.2.2. Guideline: Implement External Conflict Resolution 2.2.3. Guideline: Customize Read-During-Write Behavior 2.2.4. Guideline: Consider Power-Up State and Memory Initialization 2.2.5. Guideline: Control Clocking to Reduce Power Consumption
2.2.3. Guideline: Customize Read-During-Write Behavior x
2.2.3.1. Same-Port Read-During-Write Mode 2.2.3.2. Mixed-Port Read-During-Write Mode
2.3. Embedded Memory Features x
2.3.1. Embedded Memory Configurations 2.3.2. Mixed-Width Port Configurations
2.3.2. Mixed-Width Port Configurations x
2.3.2.1. M10K Blocks Mixed-Width Configurations
2.5. Embedded Memory Clocking Modes x
2.5.1. Clocking Modes for Each Memory Mode 2.5.2. Asynchronous Clears in Clocking Modes 2.5.3. Output Read Data in Simultaneous Read/Write 2.5.4. Independent Clock Enables in Clocking Modes
2.5.1. Clocking Modes for Each Memory Mode x
2.5.1.1. Single Clock Mode 2.5.1.2. Read/Write Clock Mode 2.5.1.3. Input/Output Clock Mode 2.5.1.4. Independent Clock Mode
2.7. Byte Enable in Embedded Memory Blocks x
2.7.1. Byte Enable Controls in Memory Blocks 2.7.2. Data Byte Output 2.7.3. RAM Blocks Operations
3. Variable Precision DSP Blocks in Cyclone® V Devices x
3.1. Features 3.2. Supported Operational Modes in Cyclone® V Devices 3.3. Resources 3.4. Design Considerations 3.5. Block Architecture 3.6. Operational Mode Descriptions 3.7. Variable Precision DSP Blocks in Cyclone® V Devices Revision History
3.4. Design Considerations x
3.4.1. Operational Modes 3.4.2. Internal Coefficient and Pre-Adder 3.4.3. Accumulator 3.4.4. Chainout Adder
3.5. Block Architecture x
3.5.1. Input Register Bank 3.5.2. Pre-Adder 3.5.3. Internal Coefficient 3.5.4. Multipliers 3.5.5. Adder 3.5.6. Accumulator and Chainout Adder 3.5.7. Systolic Registers 3.5.8. Double Accumulation Register 3.5.9. Output Register Bank
3.6. Operational Mode Descriptions x
3.6.1. Independent Multiplier Mode 3.6.2. Independent Complex Multiplier Mode 3.6.3. Multiplier Adder Sum Mode 3.6.4. 18 x 18 Multiplication Summed with 36-Bit Input Mode 3.6.5. Systolic FIR Mode
3.6.1. Independent Multiplier Mode x
3.6.1.1. 9 x 9 Independent Multiplier 3.6.1.2. 18 x 18 or 18 x 19 Independent Multiplier 3.6.1.3. 18 x 25 Independent Multiplier 3.6.1.4. 20 x 24 Independent Multiplier 3.6.1.5. 27 x 27 Independent Multiplier
3.6.2. Independent Complex Multiplier Mode x
3.6.2.1. 18 x 19 Complex Multiplier
3.6.5. Systolic FIR Mode x
3.6.5.1. 18-Bit Systolic FIR Mode 3.6.5.2. 27-Bit Systolic FIR Mode
4. Clock Networks and PLLs in Cyclone® V Devices x
4.1. Clock Networks 4.2. Cyclone® V PLLs 4.3. Clock Networks and PLLs in Cyclone® V Devices Revision History
4.1. Clock Networks x
4.1.1. Clock Resources in Cyclone® V Devices 4.1.2. Types of Clock Networks 4.1.3. Clock Sources Per Quadrant 4.1.4. Types of Clock Regions 4.1.5. Clock Network Sources 4.1.6. Clock Output Connections 4.1.7. Clock Control Block 4.1.8. Clock Power Down 4.1.9. Clock Enable Signals
4.1.2. Types of Clock Networks x
4.1.2.1. Global Clock Networks 4.1.2.2. Regional Clock Networks 4.1.2.3. Periphery Clock Networks
4.1.4. Types of Clock Regions x
4.1.4.1. Entire Device Clock Region 4.1.4.2. Regional Clock Region 4.1.4.3. Dual-Regional Clock Region
4.1.5. Clock Network Sources x
4.1.5.1. Dedicated Clock Input Pins 4.1.5.2. Internal Logic 4.1.5.3. HSSI Outputs 4.1.5.4. PLL Clock Outputs 4.1.5.5. Clock Input Pin Connections to GCLK and RCLK Networks
4.1.7. Clock Control Block x
4.1.7.1. Pin Mapping in Cyclone® V Devices 4.1.7.2. GCLK Control Block 4.1.7.3. RCLK Control Block 4.1.7.4. PCLK Control Block 4.1.7.5. External PLL Clock Output Control Block
4.2. Cyclone® V PLLs x
4.2.1. PLL Physical Counters in Cyclone® V Devices 4.2.2. PLL Locations in Cyclone® V Devices 4.2.3. PLL Migration Guidelines 4.2.4. Fractional PLL Architecture 4.2.5. PLL Cascading 4.2.6. PLL External Clock I/O Pins 4.2.7. PLL Control Signals 4.2.8. Clock Feedback Modes 4.2.9. Clock Multiplication and Division 4.2.10. Programmable Phase Shift 4.2.11. Programmable Duty Cycle 4.2.12. Clock Switchover 4.2.13. PLL Reconfiguration and Dynamic Phase Shift
4.2.4. Fractional PLL Architecture x
4.2.4.1. Fractional PLL Usage
4.2.7. PLL Control Signals x
4.2.7.1. areset 4.2.7.2. locked
4.2.8. Clock Feedback Modes x
4.2.8.1. Source Synchronous Mode 4.2.8.2. LVDS Compensation Mode 4.2.8.3. Direct Mode 4.2.8.4. Normal Compensation Mode 4.2.8.5. Zero-Delay Buffer Mode 4.2.8.6. External Feedback Mode
4.2.12. Clock Switchover x
4.2.12.1. Automatic Switchover 4.2.12.2. Automatic Switchover with Manual Override 4.2.12.3. Manual Clock Switchover 4.2.12.4. Guidelines
5. I/O Features in Cyclone® V Devices x
5.1. I/O Resources Per Package for Cyclone® V Devices 5.2. I/O Vertical Migration for Cyclone® V Devices 5.3. I/O Standards Support in Cyclone® V Devices 5.4. I/O Design Guidelines for Cyclone® V Devices 5.5. I/O Banks Locations in Cyclone® V Devices 5.6. I/O Banks Groups in Cyclone® V Devices 5.7. I/O Element Structure in Cyclone® V Devices 5.8. Programmable IOE Features in Cyclone® V Devices 5.9. On-Chip I/O Termination in Cyclone® V Devices 5.10. External I/O Termination for Cyclone® V Devices 5.11. Dedicated High-Speed Circuitries 5.12. Differential Transmitter in Cyclone® V Devices 5.13. Differential Receiver in Cyclone® V Devices 5.14. Source-Synchronous Timing Budget 5.15. I/O Features in Cyclone® V Devices Revision History
5.2. I/O Vertical Migration for Cyclone® V Devices x
5.2.1. Verifying Pin Migration Compatibility
5.3. I/O Standards Support in Cyclone® V Devices x
5.3.1. I/O Standards Support for FPGA I/O in Cyclone® V Devices 5.3.2. I/O Standards Support for HPS I/O in Cyclone® V Devices 5.3.3. I/O Standards Voltage Levels in Cyclone® V Devices 5.3.4. MultiVolt I/O Interface in Cyclone® V Devices
5.4. I/O Design Guidelines for Cyclone® V Devices x
5.4.1. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards 5.4.2. PLLs and Clocking 5.4.3. LVDS Interface with External PLL Mode 5.4.4. Guideline: Use the Same VCCPD for All I/O Banks in a Group 5.4.5. Guideline: Ensure Compatible VCCIO and VCCPD Voltage in the Same Bank 5.4.6. Guideline: VREF Pin Restrictions 5.4.7. Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing 5.4.8. Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement Rules 5.4.9. Guideline: Pin Placement for General Purpose High-Speed Signals
5.4.1. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards x
5.4.1.1. Non-Voltage-Referenced I/O Standards 5.4.1.2. Voltage-Referenced I/O Standards 5.4.1.3. Mixing Voltage-Referenced and Non-Voltage Referenced I/O Standards
5.4.2. PLLs and Clocking x
5.4.2.1. Guideline: Use PLLs in Integer PLL Mode for LVDS 5.4.2.2. Guideline: Reference Clock Restriction for LVDS Application 5.4.2.3. Guideline: Using LVDS Differential Channels
5.4.3. LVDS Interface with External PLL Mode x
5.4.3.1. Altera_PLL Signal Interface with ALTLVDS IP Core 5.4.3.2. Altera_PLL Parameter Values for External PLL Mode 5.4.3.3. Connection between Altera_PLL and ALTLVDS
5.6. I/O Banks Groups in Cyclone® V Devices x
5.6.1. Modular I/O Banks for Cyclone® V E Devices 5.6.2. Modular I/O Banks for Cyclone® V GX Devices 5.6.3. Modular I/O Banks for Cyclone® V GT Devices 5.6.4. Modular I/O Banks for Cyclone® V SE Devices 5.6.5. Modular I/O Banks for Cyclone® V SX Devices 5.6.6. Modular I/O Banks for Cyclone® V ST Devices
5.7. I/O Element Structure in Cyclone® V Devices x
5.7.1. I/O Buffer and Registers in Cyclone® V Devices
5.8. Programmable IOE Features in Cyclone® V Devices x
5.8.1. Programmable Current Strength 5.8.2. Programmable Output Slew Rate Control 5.8.3. Programmable IOE Delay 5.8.4. Programmable Output Buffer Delay 5.8.5. Programmable Pre-Emphasis 5.8.6. Programmable Differential Output Voltage 5.8.7. Open-Drain Output 5.8.8. Bus-Hold Circuitry 5.8.9. Pull-up Resistor
5.9. On-Chip I/O Termination in Cyclone® V Devices x
5.9.1. RS OCT without Calibration in Cyclone® V Devices 5.9.2. RS OCT with Calibration in Cyclone® V Devices 5.9.3. RT OCT with Calibration in Cyclone® V Devices 5.9.4. Dynamic OCT in Cyclone® V Devices 5.9.5. LVDS Input RD OCT in Cyclone® V Devices 5.9.6. OCT Calibration Block in Cyclone® V Devices
5.9.6. OCT Calibration Block in Cyclone® V Devices x
5.9.6.1. Calibration Block Locations in Cyclone® V Devices 5.9.6.2. Sharing an OCT Calibration Block on Multiple I/O Banks
5.9.6.2. Sharing an OCT Calibration Block on Multiple I/O Banks x
5.9.6.2.1. OCT Calibration Block Sharing Example
5.10. External I/O Termination for Cyclone® V Devices x
5.10.1. Single-ended I/O Termination 5.10.2. Differential I/O Termination
5.10.2. Differential I/O Termination x
5.10.2.1. Differential HSTL, SSTL, and HSUL Termination 5.10.2.2. LVDS, RSDS, SLVS, and Mini-LVDS Termination 5.10.2.3. Emulated LVDS, RSDS, and Mini-LVDS Termination 5.10.2.4. LVPECL Termination
5.11. Dedicated High-Speed Circuitries x
5.11.1. High-Speed Differential I/O Locations 5.11.2. LVDS SERDES Circuitry 5.11.3. True LVDS Buffers in Cyclone® V Devices 5.11.4. Emulated LVDS Buffers in Cyclone® V Devices
5.12. Differential Transmitter in Cyclone® V Devices x
5.12.1. Transmitter Blocks 5.12.2. Serializer Bypass for DDR and SDR Operations
5.12.1. Transmitter Blocks x
5.12.1.1. Transmitter Clocking
5.13. Differential Receiver in Cyclone® V Devices x
5.13.1. Receiver Blocks in Cyclone® V Devices 5.13.2. Receiver Mode in Cyclone® V Devices 5.13.3. Receiver Clocking for Cyclone® V Devices 5.13.4. Differential I/O Termination for Cyclone® V Devices
5.13.1. Receiver Blocks in Cyclone® V Devices x
5.13.1.1. Data Realignment Block (Bit Slip) 5.13.1.2. Deserializer
5.13.2. Receiver Mode in Cyclone® V Devices x
5.13.2.1. LVDS Receiver Mode
5.14. Source-Synchronous Timing Budget x
5.14.1. Differential Data Orientation 5.14.2. Differential I/O Bit Position 5.14.3. Transmitter Channel-to-Channel Skew 5.14.4. Receiver Skew Margin for LVDS Mode
5.14.2. Differential I/O Bit Position x
5.14.2.1. Differential Bit Naming Conventions
6. External Memory Interfaces in Cyclone® V Devices x
6.1. External Memory Performance 6.2. HPS External Memory Performance 6.3. Memory Interface Pin Support in Cyclone® V Devices 6.4. External Memory Interface Features in Cyclone® V Devices 6.5. Hard Memory Controller 6.6. External Memory Interfaces in Cyclone® V Devices Revision History
6.3. Memory Interface Pin Support in Cyclone® V Devices x
6.3.1. Guideline: Using DQ/DQS Pins 6.3.2. DQ/DQS Bus Mode Pins for Cyclone® V Devices 6.3.3. DQ/DQS Groups in Cyclone V E 6.3.4. DQ/DQS Groups in Cyclone V GX 6.3.5. DQ/DQS Groups in Cyclone V GT 6.3.6. DQ/DQS Groups in Cyclone V SE 6.3.7. DQ/DQS Groups in Cyclone V SX 6.3.8. DQ/DQS Groups in Cyclone V ST
6.4. External Memory Interface Features in Cyclone® V Devices x
6.4.1. UniPHY IP 6.4.2. External Memory Interface Datapath 6.4.3. DQS Phase-Shift Circuitry 6.4.4. PHY Clock (PHYCLK) Networks 6.4.5. DQS Logic Block 6.4.6. Dynamic OCT Control 6.4.7. IOE Registers 6.4.8. Delay Chains 6.4.9. I/O and DQS Configuration Blocks
6.4.3. DQS Phase-Shift Circuitry x
6.4.3.1. Delay-Locked Loop 6.4.3.2. DLL Reference Clock Input for Cyclone V Devices 6.4.3.3. DLL Phase-Shift
6.4.5. DQS Logic Block x
6.4.5.1. Update Enable Circuitry 6.4.5.2. DQS Delay Chain 6.4.5.3. DQS Postamble Circuitry 6.4.5.4. Half Data Rate Block
6.4.7. IOE Registers x
6.4.7.1. Input Registers 6.4.7.2. Output Registers
6.5. Hard Memory Controller x
6.5.1. Features of the Hard Memory Controller 6.5.2. Multi-Port Front End 6.5.3. Bonding Support 6.5.4. Hard Memory Controller Width for Cyclone V E 6.5.5. Hard Memory Controller Width for Cyclone V GX 6.5.6. Hard Memory Controller Width for Cyclone V GT 6.5.7. Hard Memory Controller Width for Cyclone V SE 6.5.8. Hard Memory Controller Width for Cyclone V SX 6.5.9. Hard Memory Controller Width for Cyclone V ST
6.5.2. Multi-Port Front End x
6.5.2.1. Numbers of MPFE Ports Per Device
7. Configuration, Design Security, and Remote System Upgrades in Cyclone® V Devices x
7.1. Enhanced Configuration and Configuration via Protocol 7.2. MSEL Pin Settings 7.3. Configuration Sequence 7.4. Configuration Timing Waveforms 7.5. Device Configuration Pins 7.6. Fast Passive Parallel Configuration 7.7. Active Serial Configuration 7.8. Using EPCS and EPCQ Devices 7.9. Passive Serial Configuration 7.10. JTAG Configuration 7.11. Configuration Data Compression 7.12. Remote System Upgrades 7.13. Design Security 7.14. Configuration, Design Security, and Remote System Upgrades in Cyclone® V Devices Revision History
7.3. Configuration Sequence x
7.3.1. Power Up 7.3.2. Reset 7.3.3. Configuration 7.3.4. Configuration Error Handling 7.3.5. Initialization 7.3.6. User Mode
7.4. Configuration Timing Waveforms x
7.4.1. FPP Configuration Timing 7.4.2. AS Configuration Timing 7.4.3. PS Configuration Timing
7.5. Device Configuration Pins x
7.5.1. I/O Standards and Drive Strength for Configuration Pins 7.5.2. Configuration Pin Options in the Intel® Quartus® Prime Software
7.6. Fast Passive Parallel Configuration x
7.6.1. Fast Passive Parallel Single-Device Configuration 7.6.2. Fast Passive Parallel Multi-Device Configuration 7.6.3. Transmitting Configuration Data
7.6.2. Fast Passive Parallel Multi-Device Configuration x
7.6.2.1. Pin Connections and Guidelines 7.6.2.2. Using Multiple Configuration Data 7.6.2.3. Using One Configuration Data
7.7. Active Serial Configuration x
7.7.1. DATA Clock (DCLK) 7.7.2. Active Serial Single-Device Configuration 7.7.3. Active Serial Multi-Device Configuration 7.7.4. Estimating the Active Serial Configuration Time
7.7.3. Active Serial Multi-Device Configuration x
7.7.3.1. Pin Connections and Guidelines 7.7.3.2. Using Multiple Configuration Data
7.8. Using EPCS and EPCQ Devices x
7.8.1. Controlling EPCS and EPCQ Devices 7.8.2. Evaluating Data Setup and Hold Timing Slack in AS Configuration 7.8.3. Programming EPCS and EPCQ Devices
7.8.3. Programming EPCS and EPCQ Devices x
7.8.3.1. Programming EPCS Using the JTAG Interface 7.8.3.2. Programming EPCQ Using the JTAG Interface 7.8.3.3. Programming EPCS Using the Active Serial Interface 7.8.3.4. Programming EPCQ Using the Active Serial Interface
7.9. Passive Serial Configuration x
7.9.1. Passive Serial Single-Device Configuration Using an External Host 7.9.2. Passive Serial Single-Device Configuration Using an Altera Download Cable 7.9.3. Passive Serial Multi-Device Configuration
7.9.3. Passive Serial Multi-Device Configuration x
7.9.3.1. Pin Connections and Guidelines 7.9.3.2. Using Multiple Configuration Data 7.9.3.3. Using One Configuration Data 7.9.3.4. Using PC Host and Download Cable
7.10. JTAG Configuration x
7.10.1. JTAG Single-Device Configuration 7.10.2. JTAG Multi-Device Configuration 7.10.3. CONFIG_IO JTAG Instruction
7.10.2. JTAG Multi-Device Configuration x
7.10.2.1. Pin Connections and Guidelines 7.10.2.2. Using a Download Cable
7.11. Configuration Data Compression x
7.11.1. Enabling Compression Before Design Compilation 7.11.2. Enabling Compression After Design Compilation 7.11.3. Using Compression in Multi-Device Configuration
7.12. Remote System Upgrades x
7.12.1. Configuration Images 7.12.2. Configuration Sequence in the Remote Update Mode 7.12.3. Remote System Upgrade Circuitry 7.12.4. Enabling Remote System Upgrade Circuitry 7.12.5. Remote System Upgrade Registers 7.12.6. Remote System Upgrade State Machine 7.12.7. User Watchdog Timer
7.12.5. Remote System Upgrade Registers x
7.12.5.1. Control Register 7.12.5.2. Status Register
7.13. Design Security x
7.13.1. Altera Unique Chip ID IP Core 7.13.2. JTAG Secure Mode 7.13.3. Security Key Types 7.13.4. Security Modes 7.13.5. Design Security Implementation Steps
8. SEU Mitigation for Cyclone® V Devices x
8.1. Error Detection Features 8.2. Configuration Error Detection 8.3. User Mode Error Detection 8.4. Internal Scrubbing 8.5. Specifications 8.6. Using Error Detection Features in User Mode 8.7. SEU Mitigation for Cyclone® V Devices Document Revision History
8.5. Specifications x
8.5.1. Minimum EMR Update Interval 8.5.2. Error Detection Frequency 8.5.3. CRC Calculation Time For Entire Device
8.6. Using Error Detection Features in User Mode x
8.6.1. Enabling Error Detection 8.6.2. CRC_ERROR Pin 8.6.3. Error Detection Registers 8.6.4. Error Detection Process 8.6.5. Testing the Error Detection Block
9. JTAG Boundary-Scan Testing in Cyclone® V Devices x
9.1. BST Operation Control 9.2. I/O Voltage for JTAG Operation 9.3. Performing BST 9.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry 9.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing 9.6. IEEE Std. 1149.1 Boundary-Scan Register 9.7. JTAG Boundary-Scan Testing in Cyclone® V Devices Revision History
9.1. BST Operation Control x
9.1.1. IDCODE 9.1.2. Supported JTAG Instruction 9.1.3. JTAG Secure Mode 9.1.4. JTAG Private Instruction
9.6. IEEE Std. 1149.1 Boundary-Scan Register x
9.6.1. Boundary-Scan Cells of a Cyclone® V Device I/O Pin
10. Power Management in Cyclone® V Devices x
10.1. Power Consumption 10.2. Hot-Socketing Feature 10.3. Hot-Socketing Implementation 10.4. Power-Up Sequence Recommendation for Cyclone® V Devices 10.5. Power-On Reset Circuitry 10.6. Power Management in Cyclone® V Devices Revision History
10.1. Power Consumption x
10.1.1. Dynamic Power Equation
10.5. Power-On Reset Circuitry x
10.5.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
1. Logic Array Blocks and Adaptive Logic Modules in Cyclone® V Devices
2. Embedded Memory Blocks in Cyclone® V Devices
3. Variable Precision DSP Blocks in Cyclone® V Devices
4. Clock Networks and PLLs in Cyclone® V Devices
5. I/O Features in Cyclone® V Devices
6. External Memory Interfaces in Cyclone® V Devices
7. Configuration, Design Security, and Remote System Upgrades in Cyclone® V Devices
8. SEU Mitigation for Cyclone® V Devices
9. JTAG Boundary-Scan Testing in Cyclone® V Devices
10. Power Management in Cyclone® V Devices

5.13.1.1. Data Realignment Block (Bit Slip)

Skew in the transmitted data along with skew added by the link causes channel-to-channel skew on the received serial data streams. To compensate for this channel-to-channel skew and establish the correct received word boundary at each channel, each receiver channel has a dedicated data realignment circuit that realigns the data by inserting bit latencies into the serial stream.

An optional RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each receiver independently controlled from the internal logic. The data slips one bit on the rising edge of RX_CHANNEL_DATA_ALIGN. The requirements for the RX_CHANNEL_DATA_ALIGN signal include the following items:

  • The minimum pulse width is one period of the parallel clock in the logic array.
  • The minimum low time between pulses is one period of the parallel clock.
  • The signal is an edge-triggered signal.
  • The valid data is available two parallel clock cycles after the rising edge of RX_CHANNEL_DATA_ALIGN.
Figure 110. Data Realignment TimingThis figure shows receiver output (RX_OUT) after one bit slip pulse with the deserialization factor set to 4.


The data realignment circuit can have up to 11 bit-times of insertion before a rollover occurs. The programmable bit rollover point can be from 1 to 11 bit-times, independent of the deserialization factor. Set the programmable bit rollover point equal to, or greater than, the deserialization factor—allowing enough depth in the word alignment circuit to slip through a full word. You can set the value of the bit rollover point using the IP Catalog. An optional status port, RX_CDA_MAX, is available to the FPGA fabric from each channel to indicate the reaching of the preset rollover point.

Figure 111. Receiver Data Realignment RolloverThis figure shows a preset value of four bit-times before rollover occurs. The rx_cda_max signal pulses for one rx_outclock cycle to indicate that rollover has occurred.


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