Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents locked

The locked signal output of the PLL indicates the following conditions:

  • The PLL has locked onto the reference clock.
  • The PLL clock outputs are operating at the desired phase and frequency set in the IP Catalog.

The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock has locked onto the reference clock both in phase and frequency.