Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration
ID
683375
Date
10/18/2023
Public
1. Logic Array Blocks and Adaptive Logic Modules in Cyclone® V Devices
2. Embedded Memory Blocks in Cyclone® V Devices
3. Variable Precision DSP Blocks in Cyclone® V Devices
4. Clock Networks and PLLs in Cyclone® V Devices
5. I/O Features in Cyclone® V Devices
6. External Memory Interfaces in Cyclone® V Devices
7. Configuration, Design Security, and Remote System Upgrades in Cyclone® V Devices
8. SEU Mitigation for Cyclone® V Devices
9. JTAG Boundary-Scan Testing in Cyclone® V Devices
10. Power Management in Cyclone® V Devices
2.1. Types of Embedded Memory
2.2. Embedded Memory Design Guidelines for Cyclone® V Devices
2.3. Embedded Memory Features
2.4. Embedded Memory Modes
2.5. Embedded Memory Clocking Modes
2.6. Parity Bit in Memory Blocks
2.7. Byte Enable in Embedded Memory Blocks
2.8. Memory Blocks Packed Mode Support
2.9. Memory Blocks Address Clock Enable Support
2.10. Embedded Memory Blocks in Cyclone® V Devices Revision History
4.2.1. PLL Physical Counters in Cyclone® V Devices
4.2.2. PLL Locations in Cyclone® V Devices
4.2.3. PLL Migration Guidelines
4.2.4. Fractional PLL Architecture
4.2.5. PLL Cascading
4.2.6. PLL External Clock I/O Pins
4.2.7. PLL Control Signals
4.2.8. Clock Feedback Modes
4.2.9. Clock Multiplication and Division
4.2.10. Programmable Phase Shift
4.2.11. Programmable Duty Cycle
4.2.12. Clock Switchover
4.2.13. PLL Reconfiguration and Dynamic Phase Shift
5.1. I/O Resources Per Package for Cyclone® V Devices
5.2. I/O Vertical Migration for Cyclone® V Devices
5.3. I/O Standards Support in Cyclone® V Devices
5.4. I/O Design Guidelines for Cyclone® V Devices
5.5. I/O Banks Locations in Cyclone® V Devices
5.6. I/O Banks Groups in Cyclone® V Devices
5.7. I/O Element Structure in Cyclone® V Devices
5.8. Programmable IOE Features in Cyclone® V Devices
5.9. On-Chip I/O Termination in Cyclone® V Devices
5.10. External I/O Termination for Cyclone® V Devices
5.11. Dedicated High-Speed Circuitries
5.12. Differential Transmitter in Cyclone® V Devices
5.13. Differential Receiver in Cyclone® V Devices
5.14. Source-Synchronous Timing Budget
5.15. I/O Features in Cyclone® V Devices Revision History
5.4.1. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards
5.4.2. PLLs and Clocking
5.4.3. LVDS Interface with External PLL Mode
5.4.4. Guideline: Use the Same VCCPD for All I/O Banks in a Group
5.4.5. Guideline: Ensure Compatible VCCIO and VCCPD Voltage in the Same Bank
5.4.6. Guideline: VREF Pin Restrictions
5.4.7. Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing
5.4.8. Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement Rules
5.4.9. Guideline: Pin Placement for General Purpose High-Speed Signals
5.6.1. Modular I/O Banks for Cyclone® V E Devices
5.6.2. Modular I/O Banks for Cyclone® V GX Devices
5.6.3. Modular I/O Banks for Cyclone® V GT Devices
5.6.4. Modular I/O Banks for Cyclone® V SE Devices
5.6.5. Modular I/O Banks for Cyclone® V SX Devices
5.6.6. Modular I/O Banks for Cyclone® V ST Devices
5.8.1. Programmable Current Strength
5.8.2. Programmable Output Slew Rate Control
5.8.3. Programmable IOE Delay
5.8.4. Programmable Output Buffer Delay
5.8.5. Programmable Pre-Emphasis
5.8.6. Programmable Differential Output Voltage
5.8.7. Open-Drain Output
5.8.8. Bus-Hold Circuitry
5.8.9. Pull-up Resistor
5.9.1. RS OCT without Calibration in Cyclone® V Devices
5.9.2. RS OCT with Calibration in Cyclone® V Devices
5.9.3. RT OCT with Calibration in Cyclone® V Devices
5.9.4. Dynamic OCT in Cyclone® V Devices
5.9.5. LVDS Input RD OCT in Cyclone® V Devices
5.9.6. OCT Calibration Block in Cyclone® V Devices
6.3.1. Guideline: Using DQ/DQS Pins
6.3.2. DQ/DQS Bus Mode Pins for Cyclone® V Devices
6.3.3. DQ/DQS Groups in Cyclone V E
6.3.4. DQ/DQS Groups in Cyclone V GX
6.3.5. DQ/DQS Groups in Cyclone V GT
6.3.6. DQ/DQS Groups in Cyclone V SE
6.3.7. DQ/DQS Groups in Cyclone V SX
6.3.8. DQ/DQS Groups in Cyclone V ST
6.5.1. Features of the Hard Memory Controller
6.5.2. Multi-Port Front End
6.5.3. Bonding Support
6.5.4. Hard Memory Controller Width for Cyclone V E
6.5.5. Hard Memory Controller Width for Cyclone V GX
6.5.6. Hard Memory Controller Width for Cyclone V GT
6.5.7. Hard Memory Controller Width for Cyclone V SE
6.5.8. Hard Memory Controller Width for Cyclone V SX
6.5.9. Hard Memory Controller Width for Cyclone V ST
7.1. Enhanced Configuration and Configuration via Protocol
7.2. MSEL Pin Settings
7.3. Configuration Sequence
7.4. Configuration Timing Waveforms
7.5. Device Configuration Pins
7.6. Fast Passive Parallel Configuration
7.7. Active Serial Configuration
7.8. Using EPCS and EPCQ Devices
7.9. Passive Serial Configuration
7.10. JTAG Configuration
7.11. Configuration Data Compression
7.12. Remote System Upgrades
7.13. Design Security
7.14. Configuration, Design Security, and Remote System Upgrades in Cyclone® V Devices Revision History
9.1. BST Operation Control
9.2. I/O Voltage for JTAG Operation
9.3. Performing BST
9.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
9.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
9.6. IEEE Std. 1149.1 Boundary-Scan Register
9.7. JTAG Boundary-Scan Testing in Cyclone® V Devices Revision History
6.5.3. Bonding Support
Note: Bonding is supported only for hard memory controllers configured with one port. Do not use the bonding configuration when there is more than one port in each hard memory controller.
You can bond two hard memory controllers to support wider data widths.
If you bond two hard memory controllers, the data going out of the controllers to the user logic is synchronized. However, the data going out of the controllers to the memory is not synchronized.
The bonding controllers are not synchronized and remain independent with two separate address buses and two independent command buses. These buses are calibrated separately.
If you require ECC support for a bonded interface, you must implement the ECC logic external to the hard memory controllers.
Note: A memory interface that uses the bonding feature has higher average latency. Bonding through the core fabric will also cause a higher latency.
Figure 141. Hard Memory Controllers Bonding Support in Cyclone V E A7, A5, and A9 Devices, Cyclone V GX C4, C5, C7, and C9 Devices, and Cyclone V GT D5, D7, and D9 Devices This figure shows the bonding of two opposite hard memory controllers through the core fabric.
Figure 142. Hard Memory Controllers in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6 DevicesThis figure shows hard memory controllers in the SoC devices. There is no bonding support.