Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

6.4.4. PHY Clock (PHYCLK) Networks

The PHYCLK network is a dedicated high-speed, low-skew balanced clock tree designed for a high-performance external memory interface.

The top and bottom sides of the Cyclone® V devices have up to four PHYCLK networks each. There are up to two PHYCLK networks on the left and right side I/O banks. Each PHYCLK network spans across one I/O bank and is driven by one of the PLLs located adjacent to the I/O bank.

The following figures show the PHYCLK networks available in the Cyclone® V devices.

Figure 126. PHYCLK Networks in Cyclone® V E A2 and A4 Devices

Figure 127. PHYCLK Networks in Cyclone® V GX C3 Devices

Figure 128. PHYCLK Networks in Cyclone® V E A7, A5, and A9 Devices, Cyclone V GX C4, C5, C7, and C9 Devices, and Cyclone V GT D5, D7, and D9 Devices

Figure 129.  PHYCLK Networks in Cyclone® V SE A2, A4, A5, and A6 Devices

Figure 130.  PHYCLK Networks in Cyclone® V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6 Devices