Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

9.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry

The IEEE Std. 1149.1 BST circuitry is enabled after the Cyclone® V device powers up. However for Cyclone® V SoC FPGAs, you must power up both HPS and FPGA to perform BST.

The HPS should be held in reset while performing BST to stop the I/Os being accessed or setup by the HPS.

To ensure that you do not inadvertently enable the IEEE Std. 1149.1 circuitry when it is not required, disable the circuitry permanently with pin connections as listed in the following table.

Table 115.  Pin Connections to Permanently Disable the IEEE Std. 1149.1 Circuitry for Cyclone® V Devices
JTAG Pins27 Connection for Disabling
TMS VCCPD supply of Bank 3A
TDI VCCPD supply of Bank 3A
TDO Leave open
27 The JTAG pins are dedicated. Software option is not available to disable JTAG in Cyclone® V devices.