3.5.1. Input Register Bank
The input register bank consists of data, dynamic control signals, and two sets of delay registers.
All the registers in the DSP blocks are positive-edge triggered and cleared on power up. Each multiplier operand can feed an input register or a multiplier directly, bypassing the input registers.
The following variable precision DSP block signals control the input registers within the variable precision DSP block:
In 18 x 19 mode, you can use the delay registers to balance the latency requirements when you use both the input cascade and chainout features.
The tap-delay line feature allows you to drive the top leg of the multiplier input, dataa_y0 and datab_y1 in 18 x 19 mode and dataa_y0 only in 27 x 27 mode, from the general routing or cascade chain.
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