Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Public
Document Table of Contents

5.6.5. Modular I/O Banks for Cyclone® V SX Devices

Table 46.  Modular I/O Banks for Cyclone® V SX Devices
Note: The HPS row and column I/O counts are the number of HPS-specific I/O pins on the device. Each HPS-specific pin may be mapped to several HPS I/Os.
Member Code C2 C4 C5 C6
Package U672 U672 U672 F896 U672 F896
FPGA I/O Bank 3A 16 16 16 32 16 32
3B 32 32 32 48 32 48
4A 68 68 68 80 68 80
5A 16 16 16 32 16 32
5B 16 16
HPS Row I/O Bank 6A 56 56 56 56 56 56
6B 44 44 44 44 44 44
HPS Column I/O Bank 7A 19 19 19 19 19 19
7B 22 22 22 22 22 22
7C 12 12 12 12 12 12
7D 14 14 14 14 14 14
FPGA I/O Bank 8A 13 13 13 80 13 80
Total 312 312 312 455 312 455