Cyclone V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 7/05/2022
Public
Document Table of Contents

5.7.1. I/O Buffer and Registers in Cyclone® V Devices

I/O registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output enable (OE) path for handling the OE signal to the output buffer. These registers allow faster source-synchronous register-to-register transfers and resynchronization.

Table 48.  Input and Output Paths in Cyclone® V DevicesThis table summarizes the input and output path in the Cyclone® V devices.
Input Path Output Path

Consists of:

  • DDR input registers
  • Alignment and synchronization registers
  • Half data rate blocks

Consists of:

  • Output or OE registers
  • Alignment registers
  • Half data rate blocks

You can bypass each block in the input path. The input path uses the deskew delay to adjust the input register clock delay across process, voltage, and temperature (PVT) variations.

You can bypass each block of the output and OE paths.

Figure 81. IOE Structure for Cyclone® V DevicesThis figure shows the Cyclone® V FPGA IOE structure. In the figure, one dynamic on-chip termination (OCT) control is available for each DQ/DQS group.


Did you find the information on this page useful?

Characters remaining:

Feedback Message