Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

5.13.1. Receiver Blocks in Cyclone® V Devices

The Cyclone® V differential receiver has the following hardware blocks:

  • Data realignment block (bit slip)
  • Deserializer

The following figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers, and sends a maximum of 10 bits to the internal logic.

Figure 109. Receiver Block Diagram