Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents RCLK Control Block

You can only control the clock source selection for the RCLK select block statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Intel® Quartus® Prime software.

Figure 44. RCLK Control Block for Cyclone® V Devices

You can set the input clock sources and the clkena signals for the GCLK and RCLK network multiplexers through the Intel® Quartus® Prime software using the ALTCLKCTRL IP core.

Note: When selecting the clock source dynamically using the ALTCLKCTRL IP core, choose the inputs using the CLKSELECT[0..1] signal. The inputs from the clock pins feed the inclk[0..1] ports of the multiplexer, and the PLL outputs feed the inclk[2..3] ports.