Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

1.1.4. ALM Resources

One ALM contains four programmable registers. Each register has the following ports:

  • Data
  • Clock
  • Synchronous and asynchronous clear
  • Synchronous load

Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the clock and clear control signals of an ALM register.

GPIO pins or internal logic drives the clock enable signal.

For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives directly to the outputs of an ALM.

Note: The Intel® Quartus® Prime software automatically configures the ALMs for optimized performance.
Figure 5. ALM High-Level Block Diagram for Cyclone® V Devices