4.2.8. Clock Feedback Modes
This section describes the following clock feedback modes:
- Source synchronous
- LVDS compensation
- Normal compensation
Each mode allows clock multiplication and division, phase shifting, and programmable duty cycle.
The input and output delays are fully compensated by a PLL only when using the dedicated clock input pins associated with a given PLL as the clock source.
The input and output delays may not be fully compensated in the Intel® Quartus® Prime software for the following conditions:
- When a GCLK or RCLK network drives the PLL
- When the PLL is driven by a dedicated clock pin that is not associated with the PLL
For example, when you configure a PLL in ZDB mode, the PLL input is driven by an associated dedicated clock input pin. In this configuration, a fully compensated clock path results in zero delay between the clock input and one of the clock outputs from the PLL. However, if the PLL input is fed by a non-dedicated input (using the GCLK network), the output clock may not be perfectly aligned with the input clock.
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