Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

10.1.1. Adaptive Noise Reduction IP Performance and Resources

Altera provides resource and utilization data for guidance only. The IP resources depends on the device family, compilation tool version, compilation seed randomization, and other parameters.
Table 62.  Adaptive Noise Reduction IP Performance and Resources
Device Pixels in Parallel

Enable CFA

Bits per

Color

Sample

Max Resolution ALM M20k DSP

f MAX

(MHz)

Agilex 5 speed grade 6 (A5ED065BB32AE6SR0) 1 1 10 2k 1,826 23 26 463 11
1 0 16 2k 3,159 36 50 420 11
2 1 10 4k 3,152 46 52 416 11
2 0 16 4k 5,599 71 100 406 11
Agilex 7 speed grade 2 (AGFA012R24A2E2V) 1 1 10 2k 1,979 23 26 755
1 0 16 2k 3,073 36 50 809
2 1 10 4k 3,183 46 52 809
2 0 16 4k 5,615 71 100 762
4 1 10 8k 5,974 92 104 749
4 0 16 8k 10,059 142 200 746
Arria 10 speed grade 1 (10AS066H1F34E1HG) 1 1 10 2k 1,334 34 42 455
1 0 16 2k 2,147 59 82 453
2 1 10 4k 2,167 68 84 453
2 0 16 4k 3,880 119 164 444
Cyclone 10 GX speed grade 5 (10CX220YF672E5G) 1 1 10 2k 1,326 34 42 372
1 0 16 2k 2,134 59 82 371
Stratix 10 speed grade 1 (1SX280LN2F43E1VG) 1 1 10 2k 2,113 23 42 498
1 0 16 2k 3,887 36 82 497
2 1 10 4k 3,593 46 84 498
2 0 16 4k 6,201 71 164 497
11 Restricted fMAX 321 MHz rest