Visible to Intel only — GUID: nyg1637769028434
Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter IP
8. 1D LUT IP
9. 3D LUT IP
10. Adaptive Noise Reduction IP
11. Advanced Test Pattern Generator IP
12. AXI-Stream Broadcaster IP
13. Bits per Color Sample Adapter IP
14. Black Level Correction IP
15. Black Level Statistics IP
16. Chroma Key IP
17. Chroma Resampler IP
18. Clipper IP
19. Clocked Video Input IP
20. Clocked Video to Full-Raster Converter IP
21. Clocked Video Output IP
22. Color Plane Manager IP
23. Color Space Converter IP
24. Defective Pixel Correction IP
25. Deinterlacer IP
26. Demosaic IP
27. FIR Filter IP
28. Frame Cleaner IP
29. Full-Raster to Clocked Video Converter IP
30. Full-Raster to Streaming Converter IP
31. Genlock Controller IP
32. Generic Crosspoint IP
33. Genlock Signal Router IP
34. Guard Bands IP
35. Histogram Statistics IP
36. Interlacer IP
37. Mixer IP
38. Pixels in Parallel Converter IP
39. Scaler IP
40. Stream Cleaner IP
41. Switch IP
42. Text Box IP
43. Tone Mapping Operator IP
44. Test Pattern Generator IP
45. Unsharp Mask IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO IP
51. Video Timing Generator IP
52. Vignette Correction IP
53. Warp IP
54. White Balance Correction IP
55. White Balance Statistics IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
31.4.3. Setting the VCXO hold over
31.4.4. Restarting the Genlock Controller IP
31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
31.4.7. Disturbing a Reference Clock (a cable pull)
Visible to Intel only — GUID: nyg1637769028434
Ixiasoft
29.4. Full-Raster to Clocked Video Converter Registers
The IP allows runtime configuration of parameters using the Avalon memory-mapped CPU register interface. Unless stated, all registers are 32-bit wide.
Register | Offset | Access | Description |
---|---|---|---|
CVI specific registers | |||
Reg_CVI_Legacy_0 | 0x140 | RW | Drives legacy CVI conduit output signals and returns the current values. |
Reg_CVI_Legacy_1 | 0x144 | RW | Drives legacy CVI conduit output signals and returns the current values. |
Reg_CVI_Legacy_2 | 0x148 | RW | Drives legacy CVI conduit output signals and returns the current values. |
CVO specific registers | |||
Reg_CVO_Legacy_0 | 0x14C | RW | The current value of the CVO conduit side-band signals vid_sof. |
Name | Bits | Attribute | Description |
---|---|---|---|
CVI SOF | 0 | RO | The current value of the CVI legacy signal sof. |
CVI SOF Locked | 1 | RO | The current value of the CVI legacy signal sof_locked. |
CVI Overflow | 2 | RO | The current value of the CVI legacy signal overflow. |
CVI Clipping | 3 | RO | The current value of the CVI legacy signal clipping. |
CVI Padding | 4 | RO | The current value of the CVI legacy signal padding. |
CVI refclk_div | 5 | RO | The current value of the CVI legacy signal refclk_div. |
Reserved | 7:6 | - | Reserved. |
CVI video locked | 8 | RW | Drives legacy CVI conduit signal vid_locked. |
Reserved | 15:9 | - | Reserved. |
CVI color encoding | 23:16 | RW | Drives legacy CVI conduit signal vid_color_encoding. |
CVI bit width | 31:24 | RW | Drives legacy CVI conduit signal vid_bit_width. |
Name | Bits | Attribute | Description |
---|---|---|---|
CVI vid std | Width of vid_std -1:0 | RW | Drives legacy CVI conduit signal vid_std. |
CVI HDMI duplication | 19:16 | RW | Drives legacy CVI conduit signal vid_hdmi_duplication. |
Reserved | 23:20 | - | Reserved. |
CVI HD not SD | 24 | RW | Drives legacy CVI conduit signal vid_hd_sdn. |
Reserved | 31:25 | - | Reserved. |
Name | Bits | Attribute | Description |
---|---|---|---|
Total Pixels | 15:0 | RW | Drives legacy CVI conduit signal total_sample_count. |
Total Lines | 31:16 | RW | Drives legacy CVI conduit signal total_line_count. |
Name | Bits | Attribute | Description |
---|---|---|---|
CVO SOF | 0 | RW | Drives legacy clocked video output conduit signal vid_sof. |
CVO SOF Locked | 1 | RW | Drives legacy clocked video output conduit signal vid_sof_locked. |
CVO Underflow | 2 | RW | Drives legacy clocked video output conduit signal underflow. |
CVO vco clock divide | 3 | RW | Drives legacy clocked video output conduit signal vid_vcoclk_div. |
CVO mode change | 4 | RW | Drives legacy clocked video output conduit signal vid_mode_change. |
Reserved | 15:5 | - | Reserved. |
CVO video standard | Width of vid_std+15:16 | RW | Drives legacy clocked video output conduit signal vid_std. |