Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: egt1684241064254

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

49.1. About the Video Buffer Writer IP

The IP receives frames or fields from an Intel FPGA streaming video input and stores them in external memory. The frame writer has a host Avalon memory-mapped interface to allow connection to an external memory interface and an agent Avalon memory-mapped interface to allow run-time control.

The frame writer supports:

  • Maximum frame resolutions of 16,384 by 16,384 pixels with 1 to 8 pixels in parallel and any color space
  • Writing of progressive frames or interlaced fields
  • Configurable memory packing scheme
  • Runtime location of frame or field anywhere in memory
  • Configurable interrupt on completion of frame, field, or line writes
  • Free running or single-shot mode for event capture
  • Configurable discarding of broken fields or frames
  • Automatic receiving and storing of up to 16,777,215 fields or frames contiguously in memory with no host control

The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. The Video Frame Writer IP takes resolution information from the configurable buffer set registers.

An Avalon memory-mapped interface allows you to configure buffer sets and change the operating mode at run time. You must have this interface for both full and lite variants.

For details about latency and reset behavior for the Video Frame Writer, refer to Video and Vision IPs Functional Description.