Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

10.2. Adaptive Noise Reduction IP Parameters

The IP offers run-time and compile-time parameters.
Table 63.  Adaptive Noise Reduction IP Parameters
Parameter Values Description
Video Data Format
Lite mode On The IP only supports lite mode
Input bits per color sample 8 to 16 Select the number of input bits per color sample.
Output bits per color sample 8 to 16 Select the number of output bits per color sample.
Number of color planes 1 to 4 Number of color planes processed per pixel.
Enable CFA On or off Turn on 2x2 color filter array pattern. Only applies when the number of color planes is 1.
Number of pixels in parallel 1 to 8 Select the number of pixels in parallel.
Maximum Frame Size
Maximum field width 2k, 4k, 8k, 16k, 32k, 64k Specify the maximum width of incoming frames
Kernel Size
Number of vertical taps 1, 3, 5, 7, 9, 11, 13, 15, 17 Specify the vertical size of the kernel. When enable CFA is on only values 1, 5, 9, 13 and 17 are legal.
Number of horizontal taps 1, 3, 5, 7, 9, 11, 13, 15, 17 Specify the horizontal size of the kernel. When enable CFA is on only values 1, 5, 9, 13 and 17 are legal.
General
Pipeline ready signal On or off Turn on to add extra pipeline registers to the AXI4-S tready signals
Separate clock for control interface On or off Turn on for a separate clock for the control agent interface
Debug features On or off Turn on for read back of frame info registers and debugging information registers via the control agent interface.
Figure 18. Adaptive Noise Reduction IP GUI