Video and Vision Processing Suite IP User Guide

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Date 3/30/2025
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT IP x
9.1. About the 3D LUT IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. Adaptive Noise Reduction IP x
10.1. About the Adaptive Noise Reduction IP 10.2. Adaptive Noise Reduction IP Parameters 10.3. Adaptive Noise Reduction IP Functional Description 10.4. Adaptive Noise Reduction IP Registers 10.5. Adaptive Noise Reduction IP Software API
10.1. About the Adaptive Noise Reduction IP x
10.1.1. Adaptive Noise Reduction IP Performance and Resources
10.3. Adaptive Noise Reduction IP Functional Description x
10.3.1. Adaptive Noise Reduction IP Interfaces
11. Advanced Test Pattern Generator IP x
11.1. About the Advanced Test Pattern Generator IP 11.2. Advanced Test Pattern Generator IP Parameters 11.3. Advanced Test Pattern Generator IP Functional Description 11.4. Advanced Test Pattern Generator IP Registers 11.5. Advanced Test Pattern Generator IP Software API
11.1. About the Advanced Test Pattern Generator IP x
11.1.1. Advanced Test Pattern Generator IP Performance and Resources
11.3. Advanced Test Pattern Generator IP Functional Description x
11.3.1. Test Patterns 11.3.2. Dimensions, Offsets, and Alpha Settings 11.3.3. Run-time Settings 11.3.4. Advanced Test Pattern Generator IP Interfaces
12. AXI-Stream Broadcaster IP x
12.1. About the AXI-Stream Broadcaster IP 12.2. AXI-Stream Broadcaster IP Parameters 12.3. AXI-Stream Broadcaster IP Interfaces
12.1. About the AXI-Stream Broadcaster IP x
12.1.1. AXI-Stream Broadcaster IP Features 12.1.2. AXI-Stream Broadcaster IP Performance and Resources
13. Bits per Color Sample Adapter IP x
13.1. About the Bits per Color Sample Adapter IP 13.2. Bits per Color Sample Adapter IP Parameters 13.3. Bits per Color Sample Adapter IP Dithering Functional Description 13.4. Bits per Color Sample Adapter IP Registers 13.5. Bits per Color Sample Adapter Software API
13.1. About the Bits per Color Sample Adapter IP x
13.1.1. Bits per Color Sample Adapter IP Performance and Resources
13.3. Bits per Color Sample Adapter IP Dithering Functional Description x
13.3.1. Bits per Color Sample Adapter IP Interfaces
14. Black Level Correction IP x
14.1. About the Black Level Correction IP 14.2. Black Level Correction IP Parameters 14.3. Black Level Correction IP Functional Description 14.4. Black Level Correction IP Registers 14.5. Black Level Correction IP Software API
14.1. About the Black Level Correction IP x
14.1.1. Black Level Correction IP Performance and Resources
14.3. Black Level Correction IP Functional Description x
14.3.1. Black Level Correction IP Interfaces
15. Black Level Statistics IP x
15.1. About the Black Level Statistics IP 15.2. Black Level Statistics IP Parameters 15.3. Black Level Statistics IP Interfaces 15.4. Black Level Statistics IP Registers 15.5. Black Level Statistics IP Software API
15.1. About the Black Level Statistics IP x
15.1.1. Black Level Statistics IP Performance and Resources
16. Chroma Key IP x
16.1. About the Chroma Key IP 16.2. Chroma Key IP Parameters 16.3. Chroma Key IP Interfaces 16.4. Chroma Key Replacement 16.5. Chroma Key IP Registers 16.6. Chroma Key IP Software API
16.1. About the Chroma Key IP x
16.1.1. Chroma Key IP Performance and Resources
17. Chroma Resampler IP x
17.1. About the Chroma Resampler IP 17.2. Chroma Resampler IP Parameters 17.3. Chroma Resampler IP Functional Description 17.4. Chroma Resampler IP Registers 17.5. Chroma Resampler IP Software API
17.1. About the Chroma Resampler IP x
17.1.1. Chroma Resampler Performance and Resources
17.3. Chroma Resampler IP Functional Description x
17.3.1. Chroma Resampler IP Interfaces
18. Clipper IP x
18.1. About the Clipper IP 18.2. Clipper IP Parameters 18.3. Clipper IP Interfaces 18.4. Clipper IP Registers 18.5. Clipper IP Software API
18.1. About the Clipper IP x
18.1.1. Clipper IP Performance and Resources
19. Clocked Video Input IP x
19.1. About the Clocked Video Input IP 19.2. Initializing the Clocked Video Input IP 19.3. Clocked Video Input IP Parameters 19.4. Clocked Video Input IP Interfaces 19.5. Clocked Video Input IP Registers 19.6. Clocked Video Input IP Software API
19.1. About the Clocked Video Input IP x
19.1.1. Clocked Video Input IP Features 19.1.2. Clocked Video Input IP Performance and Resources
20. Clocked Video to Full-Raster Converter IP x
20.1. About the Clocked Video to Full-Raster Converter IP 20.2. Clocked Video to Full-Raster Converter Parameters 20.3. Clocked Video to Full-Raster Converter Block Description 20.4. Clocked Video Converter to Full-Raster IP Registers
20.1. About the Clocked Video to Full-Raster Converter IP x
20.1.1. Clocked Video to Full-Raster Converter Features 20.1.2. Clocked Video to Full-Raster Converter Performance and Resources
20.3. Clocked Video to Full-Raster Converter Block Description x
20.3.1. Clocked Video to Full-Raster Converter Interfaces
21. Clocked Video Output IP x
21.1. About the Clocked Video Output IP 21.2. Clocked Video Output IP Parameters 21.3. Clocked Video Output IP Functional Description 21.4. Clocked Video Output IP Interfaces 21.5. Clocked Video Output IP Registers 21.6. Clocked Video Output IP Software API
21.1. About the Clocked Video Output IP x
21.1.1. Clocked Video Output IP Performance and Resources 21.1.2. Clocked Video Output IP Features
22. Color Plane Manager IP x
22.1. About the Color Plane Manager IP 22.2. Color Plane Manager IP Parameters 22.3. Color Plane Manager IP Functional Description 22.4. Color Plane Manager IP Registers 22.5. Color Plane Manager Software API
22.1. About the Color Plane Manager IP x
22.1.1. Color Plane Manager IP Performance and Resources
22.3. Color Plane Manager IP Functional Description x
22.3.1. Color Plane Manager IP Interfaces
23. Color Space Converter IP x
23.1. About the Color Space Converter IP 23.2. Color Space Converter IP Parameters 23.3. Color Space Converter IP Functional Description 23.4. Color Space Converter IP Registers 23.5. Color Space Converter IP Software API
23.1. About the Color Space Converter IP x
23.1.1. Color Space Converter IP Features 23.1.2. Color Space Converter IP Performance and Resources
23.3. Color Space Converter IP Functional Description x
23.3.1. Color Space Converter IP Interfaces
24. Defective Pixel Correction IP x
24.1. About the Defective Pixel Correction IP 24.2. Defective Pixel Correction IP Parameters 24.3. Defective Pixel Correction IP Functional Description 24.4. Defective Pixel Correction IP Registers 24.5. Defective Pixel Correction IP Software API
24.1. About the Defective Pixel Correction IP x
24.1.1. Defective Pixel Correction IP Performance and Resources
24.3. Defective Pixel Correction IP Functional Description x
24.3.1. Defective Pixel Correction IP Interfaces
25. Deinterlacer IP x
25.1. About the Deinterlacer IP 25.2. Deinterlacer Parameters 25.3. Deinterlacer IP Functional Description 25.4. Deinterlacer IP Registers 25.5. Deinterlacer IP Software API
25.1. About the Deinterlacer IP x
25.1.1. Deinterlacer Performance and Resources
25.3. Deinterlacer IP Functional Description x
25.3.1. Deinterlacer Interfaces
26. Demosaic IP x
26.1. About the Demosaic IP 26.2. Demosaic IP Parameters 26.3. Demosaic IP Functional Description 26.4. Demosaic IP Registers 26.5. Demosaic IP Software API
26.1. About the Demosaic IP x
26.1.1. Demosaic IP Performance and Resources
26.3. Demosaic IP Functional Description x
26.3.1. Demosaic IP Interfaces
27. FIR Filter IP x
27.1. About the FIR Filter 27.2. FIR Filter Parameters 27.3. FIR Filter IP Operation 27.4. FIR Filter Interfaces 27.5. FIR Filter Registers 27.6. FIR Filter IP Software API
27.1. About the FIR Filter x
27.1.1. FIR Filter IP Performance and Resources
27.3. FIR Filter IP Operation x
27.3.1. FIR Filter Processing 27.3.2. FIR Filter Precision 27.3.3. FIR Coefficient Specification 27.3.4. FIR Filter Symmetry 27.3.5. Result to Output Data Type Conversion
27.3.4. FIR Filter Symmetry x
27.3.4.1. No Symmetry 27.3.4.2. Horizontal Symmetry 27.3.4.3. Vertical Symmetry 27.3.4.4. Horizontal and Vertical Symmetry 27.3.4.5. Diagonal Symmetry
28. Frame Cleaner IP x
28.1. About the Frame Cleaner IP 28.2. Frame Cleaner IP Parameters 28.3. Frame Cleaner IP Functional Description 28.4. Frame Cleaner IP Interfaces 28.5. Frame Cleaner IP Registers 28.6. Frame Cleaner IP Software API
28.1. About the Frame Cleaner IP x
28.1.1. Frame Cleaner IP Performance and Resources
29. Full-Raster to Clocked Video Converter IP x
29.1. About the Full-Raster to Clocked Video Converter 29.2. Full Raster to Clocked Video Converter Parameters 29.3. Full-Raster to Clocked Video Converter Block Description 29.4. Full-Raster to Clocked Video Converter Registers
29.1. About the Full-Raster to Clocked Video Converter x
29.1.1. Full-Raster to Clocked Video Converter Features 29.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
29.3. Full-Raster to Clocked Video Converter Block Description x
29.3.1. Full Raster to Clocked Video Converter Interfaces
30. Full-Raster to Streaming Converter IP x
30.1. About the Full-Raster to Streaming Converter IP 30.2. Full-Raster to Streaming Converter Parameters 30.3. Full-Raster to Streaming Converter Block Description
30.1. About the Full-Raster to Streaming Converter IP x
30.1.1. Full-Raster to Streaming Converter Features 30.1.2. Full-Raster to Streaming Converter Performance and Resources
30.3. Full-Raster to Streaming Converter Block Description x
30.3.1. Full-Raster to Streaming Converter Interfaces
31. Genlock Controller IP x
31.1. About the Genlock Controller IP 31.2. Genlock Controller IP Parameters 31.3. Genlock Controller IP Functional Description 31.4. Using Genlock Controller IP Software 31.5. Genlock Controller IP Registers 31.6. Genlock Controller IP Software API
31.1. About the Genlock Controller IP x
31.1.1. Genlock Controller IP Performance and Resources
31.3. Genlock Controller IP Functional Description x
31.3.1. Genlock Controller IP Interfaces
31.4. Using Genlock Controller IP Software x
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 31.4.3. Setting the VCXO hold over 31.4.4. Restarting the Genlock Controller IP 31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 31.4.7. Disturbing a Reference Clock (a cable pull)
32. Generic Crosspoint IP x
32.1. About the Generic Crosspoint IP 32.2. Generic Crosspoint IP Parameters 32.3. Generic Crosspoint IP Interfaces 32.4. Generic Crosspoint IP Registers 32.5. Generic Crosspoint IP Software API
32.1. About the Generic Crosspoint IP x
32.1.1. Generic Crosspoint IP Features 32.1.2. Generic Crosspoint Performance and Resources
33. Genlock Signal Router IP x
33.1. About the Genlock Signal Router IP 33.2. Genlock Signal Router IP Parameters 33.3. Genlock Signal Router IP Interfaces 33.4. Genlock Signal Router IP Registers 33.5. Genlock Signal Router IP Software API
33.1. About the Genlock Signal Router IP x
33.1.1. Genlock Signal Router IP Features 33.1.2. Genlock Signal Router IP Performance and Resources
34. Guard Bands IP x
34.1. About the Guard Bands IP 34.2. Guard Bands IP Parameters 34.3. Guard Bands IP Interfaces 34.4. Guard Bands IP Registers 34.5. Guard Bands IP Software API
34.1. About the Guard Bands IP x
34.1.1. Guard Bands IP Performance and Resources
35. Histogram Statistics IP x
35.1. About the Histogram Statistics IP 35.2. Histogram Statistics IP Parameters 35.3. Histogram Statistics IP Interfaces 35.4. Histogram Statistics IP Registers 35.5. Histogram Statistics IP Software API
35.1. About the Histogram Statistics IP x
35.1.1. Histogram Statistics IP Performance and Resources
36. Interlacer IP x
36.1. About the Interlacer IP 36.2. Interlacer IP Parameters 36.3. Interlacer IP Functional Description 36.4. Interlacer IP Registers 36.5. Interlacer IP Software API
36.1. About the Interlacer IP x
36.1.1. Interlacer IP Performance and Resources
36.3. Interlacer IP Functional Description x
36.3.1. Interlacer IP Interfaces
37. Mixer IP x
37.1. About the Mixer IP 37.2. Mixer IP Parameters 37.3. Mixer IP Functional Description 37.4. Mixer IP Registers 37.5. Mixer IP Software API
37.1. About the Mixer IP x
37.1.1. Mixer IP Performance and Resources
37.3. Mixer IP Functional Description x
37.3.1. Mixer IP Interfaces
38. Pixels in Parallel Converter IP x
38.1. About the Pixels in Parallel Converter IP 38.2. Pixels in Parallel Converter IP Parameters 38.3. Pixels in Parallel Converter Interfaces 38.4. Pixels in Parallel Converter Registers 38.5. Pixels in Parallel Converter IP Software API
38.1. About the Pixels in Parallel Converter IP x
38.1.1. Pixels in Parallel Converter IP Performance and Resources
39. Scaler IP x
39.1. About the Scaler 39.2. Scaler IP Parameters 39.3. Scaler IP Functional Description 39.4. Scaler IP Registers 39.5. Scaler IP Software API
39.1. About the Scaler x
39.1.1. Scaler IP Performance and Resources
39.2. Scaler IP Parameters x
39.2.1. Scaler Maximum Resolution
39.3. Scaler IP Functional Description x
39.3.1. Coefficient Selection 39.3.2. Coefficient Quantization 39.3.3. Filter Behavior at Edge Boundaries 39.3.4. Partial Frame Scaling 39.3.5. 422 and 420 Chroma Sampled Data Scaling 39.3.6. Scaler IP Interfaces
39.3.1. Coefficient Selection x
39.3.1.1. Updating Scaler IP Runtime Coefficients
40. Stream Cleaner IP x
40.1. About the Stream Cleaner IP 40.2. Stream Cleaner IP Parameters 40.3. Stream Cleaner IP Functional Description
40.1. About the Stream Cleaner IP x
40.1.1. Stream Cleaner IP Performance and Resources
40.3. Stream Cleaner IP Functional Description x
40.3.1. Stream Cleaner IP Interfaces
41. Switch IP x
41.1. About the Switch IP 41.2. Switch IP Parameters 41.3. Switch IP Functional Description 41.4. Switch IP Registers 41.5. Switch IP Software API
41.1. About the Switch IP x
41.1.1. Switch IP Performance and Resources
41.3. Switch IP Functional Description x
41.3.1. Switch IP Latency 41.3.2. Switch IP Interfaces
42. Text Box IP x
42.1. About the Text Box IP 42.2. Text Box IP Parameters 42.3. Text Box IP Functional Description 42.4. Text Box IP Registers 42.5. Text Box IP Software API
42.1. About the Text Box IP x
42.1.1. Text Box IP Performance and Resources
42.3. Text Box IP Functional Description x
42.3.1. Writing Text at Run Time with Double Buffering 42.3.2. Writing Text at Run Time without Double Buffering 42.3.3. Text Box IP Interfaces
43. Tone Mapping Operator IP x
43.1. About the Tone Mapping Operator IP 43.2. TMO IP Parameters 43.3. TMO IP Block Description 43.4. TMO IP Registers 43.5. TMO IP Software API
43.1. About the Tone Mapping Operator IP x
43.1.1. TMO IP Features 43.1.2. TMO IP Performance and Resource Utilization
43.3. TMO IP Block Description x
43.3.1. TMO IP Interfaces 43.3.2. TMO IP Latency
44. Test Pattern Generator IP x
44.1. About the Test Pattern Generator IP 44.2. Test Pattern Generator IP Parameters 44.3. Test Pattern Generator IP Functional Description 44.4. Test Pattern Generator IP Registers 44.5. Test Pattern Generator IP Software API
44.1. About the Test Pattern Generator IP x
44.1.1. Test Pattern Generator IP Performance and Resources
44.3. Test Pattern Generator IP Functional Description x
44.3.1. Test Patterns 44.3.2. Output Subsampling and Color Space 44.3.3. Run-time Settings 44.3.4. Test Pattern Generator IP Interfaces
45. Unsharp Mask IP x
45.1. About the Unsharp Mask IP 45.2. Unsharp Mask IP Parameters 45.3. Unsharp Mask IP Functional Description 45.4. Unsharp Mask IP Registers 45.5. Unsharp Mask IP Software API
45.1. About the Unsharp Mask IP x
45.1.1. Unsharp Mask IP Performance and Resources
45.3. Unsharp Mask IP Functional Description x
45.3.1. Unsharp Mask IP Interfaces
46. Video and Vision Monitor Intel FPGA IP x
46.1. About the Video and Vision Monitor IP 46.2. Video and Vision Monitor IP Parameters 46.3. Video and Vision Monitor IP Functional Description 46.4. Video and Vision Monitor IP Registers 46.5. Video and Vision Monitor Software API
46.1. About the Video and Vision Monitor IP x
46.1.1. Video and Vision Monitor IP Performance and Resources
46.3. Video and Vision Monitor IP Functional Description x
46.3.1. Video and Vision Monitor IP Interfaces
47. Video Frame Buffer IP x
47.1. About the Video Frame Buffer IP 47.2. Video Frame Buffer IP Parameters 47.3. Video Frame Buffer IP Functional Description 47.4. Video Frame Buffer IP Registers 47.5. Video Frame Buffer IP Software API
47.1. About the Video Frame Buffer IP x
47.1.1. Video Frame Buffer Performance and Resources
47.3. Video Frame Buffer IP Functional Description x
47.3.1. Video Frame Buffer IP Interfaces
48. Video Frame Reader Intel FPGA IP x
48.1. About the Video Frame Reader IP 48.2. Video Frame Reader IP Parameters 48.3. Video Frame Reader IP Functional Description 48.4. Video Frame Reader IP Registers 48.5. Video Frame Reader IP Software API
48.1. About the Video Frame Reader IP x
48.1.1. Video Frame Reader IP Performance and Resources
48.3. Video Frame Reader IP Functional Description x
48.3.1. Video Frame Reader IP Interfaces
49. Video Frame Writer Intel FPGA IP x
49.1. About the Video Buffer Writer IP 49.2. Video Frame Writer IP Parameters 49.3. Video Frame Writer IP Functional Description 49.4. Video Frame Writer IP Registers 49.5. Video Frame Writer IP Software API
49.1. About the Video Buffer Writer IP x
49.1.1. Video Frame Writer IP Performance and Resources
49.3. Video Frame Writer IP Functional Description x
49.3.1. Video Frame Writer IP Interfaces
50. Video Streaming FIFO IP x
50.1. About the Video Streaming FIFO IP 50.2. Video Streaming FIFO IP Parameters 50.3. Video Streaming FIFO IP Interfaces
50.1. About the Video Streaming FIFO IP x
50.1.1. Video Streaming FIFO IP Performance and Resources
51. Video Timing Generator IP x
51.1. About the Video Timing Generator IP 51.2. Video Timing Generator IP Parameters 51.3. Video Timing Generator IP Functional Description 51.4. Video Timing Generator IP Interfaces 51.5. Video Timing Generator IP Registers 51.6. Video Timing Generator IP Software API
51.1. About the Video Timing Generator IP x
51.1.1. Video Timing Generator IP Features 51.1.2. Video Timing Generator IP Performance and Resources
52. Vignette Correction IP x
52.1. About the Vignette Correction IP 52.2. Vignette Correction IP Parameters 52.3. Vignette Correction IP Interfaces 52.4. Vignette Correction IP Registers 52.5. Vignette Correction IP Software API
52.1. About the Vignette Correction IP x
52.1.1. Vignette Correction IP Performance and Resources
53. Warp IP x
53.1. About the Warp IP 53.2. Warp IP Parameters 53.3. Warp IP Block Description 53.4. Warp IP Registers 53.5. Warp IP Software API
53.1. About the Warp IP x
53.1.1. Warp IP Features 53.1.2. Warp IP Performance and Resource Utilization
53.3. Warp IP Block Description x
53.3.1. Block Cache Tool 53.3.2. Warp IP Interfaces 53.3.3. Warp IP Latency 53.3.4. External Memory for Warp IP
53.5. Warp IP Software API x
53.5.1. Using Warp IP Software 53.5.2. Warp IP Software Code Examples
54. White Balance Correction IP x
54.1. About the White Balance Correction IP 54.2. White Balance Correction IP Parameters 54.3. White Balance Correction IP Functional Description 54.4. White Balance Correction IP Registers 54.5. White Balance Correction IP Software API
54.1. About the White Balance Correction IP x
54.1.1. White Balance Correction IP Performance and Resources
54.3. White Balance Correction IP Functional Description x
54.3.1. White Balance Correction IP Interfaces
55. White Balance Statistics IP x
55.1. About the White Balance Statistics IP 55.2. White Balance Statistics IP Parameters 55.3. White Balance Statistics IP Interfaces 55.4. White Balance Statistics IP Registers 55.5. White Balance Statistics IP Software API
55.1. About the White Balance Statistics IP x
55.1.1. White Balance Statistics IP Performance and Resources
56. Design Security x
56.1. Memory Subsystems 56.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter IP
8. 1D LUT IP
9. 3D LUT IP
10. Adaptive Noise Reduction IP
11. Advanced Test Pattern Generator IP
12. AXI-Stream Broadcaster IP
13. Bits per Color Sample Adapter IP
14. Black Level Correction IP
15. Black Level Statistics IP
16. Chroma Key IP
17. Chroma Resampler IP
18. Clipper IP
19. Clocked Video Input IP
20. Clocked Video to Full-Raster Converter IP
21. Clocked Video Output IP
22. Color Plane Manager IP
23. Color Space Converter IP
24. Defective Pixel Correction IP
25. Deinterlacer IP
26. Demosaic IP
27. FIR Filter IP
28. Frame Cleaner IP
29. Full-Raster to Clocked Video Converter IP
30. Full-Raster to Streaming Converter IP
31. Genlock Controller IP
32. Generic Crosspoint IP
33. Genlock Signal Router IP
34. Guard Bands IP
35. Histogram Statistics IP
36. Interlacer IP
37. Mixer IP
38. Pixels in Parallel Converter IP
39. Scaler IP
40. Stream Cleaner IP
41. Switch IP
42. Text Box IP
43. Tone Mapping Operator IP
44. Test Pattern Generator IP
45. Unsharp Mask IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO IP
51. Video Timing Generator IP
52. Vignette Correction IP
53. Warp IP
54. White Balance Correction IP
55. White Balance Statistics IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide

28.5. Frame Cleaner IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 503.  Frame Cleaner IP Control Registers

In the software API these register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_CLEANER as appropriate and with an optional REG suffix

Address Register Access Description
Parameterization Registers
0x0000 PROD_ID RO

Read this register to retrieve the frame cleaner product ID.

This register always returns 0x6AF7_023E.

0x0004 VERSION RO

Read this register to retrieve the IP version information.

0x0008 LITE_MODE RO

Read this register to determine if lite mode is on.

This register returns 1 if lite mode is on and 0 if lite mode is off

0x000C DEBUG_ENABLED RO

Read this register to determine if you turn on Debug features.

This register returns 1 if you turn on Debug features and 0 otherwise

0x0010 USE_CUSTOM_MIN_MAX RO

Read this register to determine if the custom resolution guard bands are on.

This register returns 1 if custom resolution guard bands are on, and 0 otherwise
0x0014 MIN_WIDTH RO Read this register to determine the minimum supported field width
0x0018 MAX_WIDTH RO Read this register to determine the maximum supported field width
0x001C MIN_HEIGHT RO Read this register to determine the minimum supported field height
0x0020 MAX_HEIGHT RO Read this register to determine the maximum supported field height
0x0024 to 0x011F unused
Table 504.  Control and debugging registers

Refer to Image Information Control Packets in the Intel FPGA Streaming Video Protocol Specification, for more details of these registers

Address Register Access 92 Description
Lite Full
0x0120 IMG_INFO_WIDTH RW RO

When you turn on lite, use this register to set the expected width of incoming video fields.

When you turn off lite and turn on Debug features, this register returns the width that the frame cleaner derives from information in the image information control packet.

0x0124 IMG_INFO_HEIGHT RW RO

When you turn on lite, use this register to set the expected height of incoming video fields.

When you turn off lite and turn on Debug features, this register returns the height that the frame cleaner derives from information in the image information control packet.

0x0128 IMG_INFO_INTERLACE - RO When you turn off lite and turn on Debug features, this register returns the interlace nibble that the frame cleaner derives from information in the image information control packet. Unused in lite mode.
0x012C Reserved - - Reserved
0x0130 IMG_INFO_COLORSPACE - RO When you turn off lite and turn on Debug features, this register returns the color space that the frame cleaner derives from information in the image information control packet. Unused in lite mode.
0x0134 IMG_INFO_SUBSAMPLING - RO When you turn off lite and turn on Debug features, this register returns the subsampling that the frame cleaner derives from information in the image information control packet. Unused in lite mode.
0x0138 IMG_INFO_COSITING - RO When you turn off lite and turn on Debug features, this register returns the cositing that the frame cleaner derives from information in the image information control packet. Unused in lite mode.
0x013C IMG_INFO_FIELD_COUNT - RO When you turn off lite and turn on Debug features, this register returns the field count that the frame cleaner derives from information in the image information control packet. Unused in lite mode.
0x0138 to 0x013C unused
0x0140 STATUS RO  

Bit 0 : Status bit.

1 = frame cleaner is processing a video field, 0 otherwise. For other bits, see Table 21

0x0144

FIELD_NUM

RO   When you turn off lite and turn on Debug features, reads to this register return the field number value from the most recently received end of field control packet.
0x0148 FIELD_COUNT RO   When you turn on Debug features, reads to this register return the total number of fields received since the debug counts were last reset.
0x014C CLIPPED_FIELD_COUNT RO   When you turn on Debug features, reads to this register return the number of fields that have been clipped to match their expected size since the debug counts were last reset.
0x0150 PADDED_FIELD_COUNT RO   When you turn on Debug features, reads to this register return the number of fields that have been padded to match their expected size since the debug counts were last reset.
0x0154 PREV_FIELD_LINE_COUNT RO   When you turn on Debug features, reads to this register return the number of lines in the most recently completed field.
0x0158 PREV_FIELD_LINE_WIDTH RO   When you turn on Debug features, reads to this register return the number of pixels in the final line of the most recently completed field.
0x015C DEBUG_RESET RW   Write any value to this register to reset all debug counts to 0.

Register Bit Descriptions

Table 505.  PROD_ID
Name Bits Description
Frame cleaner product ID 31:0 This register always returns 0x6AF7_023E.
Table 506.  VERSION
Name Bits Description
Register map version 7:0 Register map version.
IP patch revision 15:8 -
IP update revision 23:16 Updated when the IP version changes.
IP major revision 31:24 Updated when the IP version changes.
Table 507.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 31:0 Returns 1 if lite mode is on and 0 otherwise
Table 508.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 31:0 Returns 1 if debug features is on and 0 otherwise
Table 509.  USE_CUSTOM_MIN_MAX
Name Bits Description
Use custom min max 31:0 Returns 1 if custom minimum and maximum resolution checks are enabled
Table 510.  MIN_WIDTH
Name Bits Description
Min width 31:0 Minimum output field width
Table 511.  MAX_WIDTH
Name Bits Description
Max width 31:0 Maximum output field width
Table 512.  MIN_HEIGHT
Name Bits Description
Min height 31:0 Minimum output field height

Table 513.  MAX_HEIGHT
Name Bits Description
Max height 31:0 Maximum output field height
Table 514.   IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

For lite parameterizations, write to this register to set the expected width of the incoming video fields.

For full parameterizations with debug features enabled, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 515.  IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

For lite parameterizations, write to this register to set the expected height of the incoming video fields.

For full parameterizations with debug features enabled, this register reads the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 516.  IMG_INFO_INTERLACE
Name Bits Description
IntlaceNibble bits 3:0

For lite parameterizations, this register has no function.

For full parameterizations with debug features enabled, this register returns the intlaceNibble field from the most recently received image information packet .

unused 31:4 Unused.
Table 517.   IMG_INFO_COLORSPACE
Name Bits Description
CSP code bits 6:0

For lite parameterizations, this register has no function.

For full parameterizations with debug features enabled, this register returns the 7 bit CSP field from the most recently received image information packet .

unused 31:7 Unused.
Table 518.  IMG_INFO_SUBSAMPLING
Name Bits Description
SubSa code bits 1:0

For lite parameterizations this register has no function.

For full parameterizations with debug features enabled, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 519.  IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0

For lite parameterizations, this register has no function.

For full parameterizations with debug features enabled, this register returns the COSITE field from the most recently received image information packet.

unused 31:2 Unused.
Table 520.  IMG_INFO_FIELD_COUNT
Name Bits Description
Count bits 6:0

For lite parameterizations, this register has no function.

For full parameterizations with debug features enabled, this register returns the 7 bit FIELD_COUNT field from the most recently received image information packet.

unused 31:7 Unused.
Table 521.  STATUS
Name Bits Description
Status bit 0 1 = frame cleaner is processing a video field, 0 otherwise.
Field clipping bit 1 1 = current field is being clipped, 0 otherwise
Field padding bit 2 1 = current field is being padded, 0 otherwise
Previous field clipped 3 1 = previous field was clipped, 0 otherwise
Previous field padded 4 2 = previous field was padded, 0 otherwise
unused 31:5 Unused.
Table 522.  FIELD_NUM
Name Bits Description
Field num 31:0 Field number value taken from the most recently received eof control packet
Table 523.  FIELD_COUNT
Name Bits Description
Field count 31:0 Number of fields received since last debug reset
Table 524.   CLIPPED_FIELD_COUNT
Name Bits Description
Clipped field count 31:0 Number of fields clipped since last debug reset
Table 525.  PADDED_FIELD_COUNT
Name Bits Description
Padded field count 31:0 Number of fields padded since last debug reset
Table 526.   PREV_FIELD_LINE_COUNT
Name Bits Description
Previous field line count 31:0 Number of lines in last completed field
Table 527.  PREV_FIELD_LINE_WIDTH
Name Bits Description
Previous field line width 31:0 Number of pixels in the final line of the previous field
Table 528.  DEBUG_RESET
Name Bits Description
unused 31:0 Unused.
92

You must turn on Debug features to read the values stored in these registers. If Debug features is off, reads to these registers return undefined data. The only exception is the STATUS register, the value of which you can always read.

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