Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: slk1639651345489

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

39.1. About the Scaler

The Scaler Intel FPGA IP resizes the fields in an Intel FPGA streaming video compliant input to produce output fields of a different height and or width. The IP supports both full and lite variants of interface protocol. The scaler offers three algorithms for resizing images: nearest neighbor, bilinear and polyphase. The three algorithms offer three cost versus quality options. Nearest neighbor offers the lowest FPGA resource cost and the lowest output image quality and polyphase offers the highest quality at the highest cost.

The scaler can resize an incoming video field to produce an output field of any size, restricted only by defined minimum and maximum widths and heights. You set the desired output field width and height at runtime via the register map (if the Avalon memory-mapped control agent interface is enabled), or via fixed parameters (if the Avalon memory-mapped control agent interface is not enabled). Full variants define the input field width and height by the image info packets received at the input interface. Lite variants define the input field width and height via the register map. With defined input and output widths and heights, the scaler applies the correct horizontal and vertical scaling ratios (which may be different).

The following bounds apply to the input and output field widths.

  • Input field width must be less than or equal to the value set in the maximum input field width parameter.
  • Output field width must be less than or equal to the value set in the maximum output field width parameter
  • Output field width must be greater than or equal to the value set in the number of pixels in parallel parameter

You may also choose to turn off scaling in the horizontal or vertical directions if either is not required. In this case, the output width or height is unaltered, regardless of the settings in the register map. Also, the scaler only supports scaling for video with 4:4:4 chroma siting. Full variants assert the error flag for any of these restrictions.