Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: bhc1411020070329

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

27.3.3. FIR Coefficient Specification

You can specify the FIR filter IP filtering operation coefficients as fixed values that the IP applies on reset if Use memory initialization coefficients file is on. Also, you can specify them at run time when you turn on Memory-mapped control interface and Update coefficients at run time.

The IP requires you to define a fixed-point type for the coefficients. The user-entered coefficients (shown as white boxes in the parameter editor) are rounded to fit in the chosen coefficient fixed-point type (shown as purple boxes in the parameter editor).

  • For run-time editable coefficients, you must enter the desired coefficient values through an Avalon memory-mapped agent control interface at run time, and you can update the coefficient values as often as once per frame.
    Note: Without enabling the coefficient initialization file, the coefficient values all revert to undefined after every reset, so you must initialize coefficients at least once on start-up.
  • To keep the register map as small as possible and to reduce complexity in the hardware, the IP reduces the number of coefficients that it edits at run time when you turn on any of the symmetric modes.
  • For T unique coefficient values after symmetry, the register map contains T addresses into which you should write coefficients, starting at address 7 and finishing at T+ 6.

Fixed Coefficient

For fixed coefficients, you specify the values for the coefficients with a comma-separated .csv text file. The selected coefficient values take effect immediate effect at reset.

Regardless of the symmetry mode, the text file must contain a full listing of all the coefficients in the N×M array i.e. the file must always contain N×M comma-separated values. When the .csv file is parsed in Platform Designer to create the list of compile time coefficients, the IP checks the values entered against the selected symmetry mode and provides warnings if the coefficients are not symmetric across the selected axes. The values specified in the .csv file must be in their unquantized format. For example, if you want a value of 1.7 for a given coefficient, the value in the file should be 1.75. When the file is parsed in Platform Designer, the coefficients automatically quantize according to the precision you specify.

Note: The quantization process selects the closest value available in the given precision format. If you select the coefficients arbitrarily without reference to the available precision, the quantized value may differ from the desired value.

Run-time Editable Coefficients

To keep the register map as small as possible and to reduce complexity in the hardware, the number of coefficients that are edited at run time is reduced when you turn on any of the symmetric modes.

If the IP has T unique coefficient values after symmetry, the register map contains T addresses into which you should write coefficients, starting at address 0x200 and finishing at 0x200 + (4*(T-1)).

Write coefficient index 0 (as described in the symmetry section) to address 0x200. Then write each successively indexed coefficient at each following address. The updated coefficient set takes effect immediately. To avoid the IP updating coefficients in the middle of a frame, Intel recommends reading bit 3 of the status register to check that the algorithmic core is idle before writing new coefficients.

Note: The coefficient values you write to the register map must be in prequantized format as the hardware cost to implement quantization on floating point values is prohibitive.