Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: cpj1716890602552

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

11.1. About the Advanced Test Pattern Generator IP

The IP produces an Intel FPGA Streaming Video compliant lite or full variant output stream. Each frame or field contains between two and eight test patterns with varying dimensions, offsets, and transparencies.

You can adjust at run time the dimensions, offsets, and transparency of test patterns, output video resolution, and individual test pattern configuration, if you turn on Memory-mapped control interface.

The IP:

  • Produces progressive or interlaced video frames or fields with resolutions up to 16384 by 16384 pixels, with 1-8 pixels in parallel in most cases.
  • Supports outputs with either RGB, YCbCr or monochrome color spaces, with 4:4:4, 4:2:2 or 4:2:0 subsampling.
  • Produces output on request, allowing for debugging of a video processing system.

This IP is the equivalent of multiple Test Pattern Generator IP instances feeding into the Mixer IP, with unified parameters and run-time control settings.

To blend multiple test patterns on the same output, instantiate this IP not the Test Pattern Generator IP. For only a single test pattern at any one time, use the Test Pattern Generator IP.