Visible to Intel only — GUID: rqr1685108249262
Ixiasoft
Visible to Intel only — GUID: rqr1685108249262
Ixiasoft
46.3. Video and Vision Monitor IP Functional Description
When using the full variant of the Intel FPGA Streaming Video interface protocol, the Video and Vision Monitor IP searches the incoming video stream for image information packets. The IP decodes the image information packets and then produces the contents of the last image information packet that you receive via the register map. The Image Information packets also specify the expected resolution for each incoming video frame. The IP counts the number of pixels in each line and the number of lines in each frame. Based on the values of these counters and the expected frame size, the IP keeps a count of the number of frames that match and do not match their expected sizes. The IP also counts the number of frames for which the following end-of-field packets assert their broken frame flag. The IP reports all these values to you via the register map. You can also reset the frame counts at any time by writing to an address in the register map.
Lite variants of the Intel FPGA Streaming Video interface protocol have no image information packets in the incoming stream to provide details of the expected frame size. You must supply this information via the register map. Lite variants also have no end-of-field packets, so this counter is not when Lite mode is on. Other than these differences, the behavior of the IP is the same as with the full variant of the protocol.
When the IP and its interfaces are parameterized for a single pixel in parallel, the IP can count the exact number of pixels in each line. The Intel FPGA Streaming Video protocol does not indicate that any of the pixels are unused on the final data beat of each packet when interfaces are parameterized for multiple pixels in parallel. Therefore, the IP cannot exactly count the number of pixels in each line when the number of pixels in parallel is greater than 1. It can count the number of beats of data in the packet and, based on this value, provide an upper and lower bound on the number of pixels.
pixels_in_parallel x (data_beats-1) + 1 <= number_of_pixels <= pixels_in_parallel x data_beats
The IP reports two-line length values to the register map:
- The minimum number of pixels in any line packet for the most recent frame, taken from the lower bound count of the number of pixels for each line.
- The maximum number of pixels in any line packet for the most recent frame, taken from the upper bound count of the number of pixels for each line.
If the IP is parameterized for 1 pixel in parallel, for frames that match their specified dimensions both these reported width values match the specified width. If the IP is parameterized for multiple pixels in parallel, the maximum and minimum line lengths have different values but adhere to the following constraints for frames that match their sizes.
expected_width – pixels_in_parallel < minimum_width <= expected_width
expected_width <= maximum_width < expected_width + pixels_in_parallel
The IP checks these constraints when deciding if each frame has to match its expected dimensions.