Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: qxl1640089098083

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

1.4. Lite versus Full IP Variants

Most video and vision processing IPs support both full and lite variants of the Intel FPGA streaming video protocol. You should choose which protocol variant (and therefore which parameterization of the IPs) is most suitable for your end application. Some of the IPs only use the lite variant of the protocol. Therefore, they do not pass control information along the streaming interface.

For the full variants, the IPs transmit some control information together with video data over the streaming interfaces. For the lite variants, write all the control information to IPs using a processor interface.

You may still select run-time control via a processor interface when using the full variant of IPs (for example, to update clipper offsets or mixer settings). The control information about the size and type of incoming video is always handled automatically using streamed control packets.

You can turn on or off lite mode in the GUI for most of the Intel video and vision processing IPs. When off, the IP is a full variant. You can interface between full and lite variants of IPs using the protocol converter IP. However, system design is easier if a video pipeline standardizes on one version of the protocol.

When choosing between full and lite consider the following advantages:

For full IP variants:

  • Ease of use. Full variants of the IPs handle more of the system control aspects automatically.
  • Video and Image Processing Suite interoperability or upgradeability. Interfacing or modifying existing systems based around the Video and Image Processing Suite IPs to the full variants is easier, as these handle video in a similar way.

For lite IP variants:

  • Building a system primarily using one of the Warp, 3D LUT or TMO IPs or a system requiring interoperability with third-party AXI-Stream video steaming IP. The Warp, 3D LUT, and TMO IPs use the lite variant of the protocol and do not pass control along the streaming interface.
  • Device area. Expect to save 100-200 ALMs per IP for lite variants.
Figure 1. Full and lite benefits radar diagram For example, lite variants are better for device area (lower area).

Regenerate IPs with either version of the protocol and compare overall system fMAX and area before deciding.