Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

44.1.1. Test Pattern Generator IP Performance and Resources

Intel provides resource and utilization data for guidance. The IP resource utilization depends on the device family, number of supported bits per sample, pixels in parallel, number of test patterns.
Table 827.  Test Pattern Generator IP Performance and ResourcesThe table shows ALM usage and fMAX for a design with 10 bits per color sample, 2 pixels in parallel, 3 test patterns (bars, constant color and SDI pathological).
Target device ALMs fMAX (MHz)
Agilex™ 7 speed grade 2 (AGFA012R24A2E2V) 725 908
Intel Arria 10 speed grade 1 (10AS066H1F34E1HG) 655 594
Intel Cyclone 10 GX speed grade 5 (10CX220YF672E5G) 656 513
Intel Stratix 10 GX speed grade 1 (1SX280LN2F43E1VG) 735 749
Table 828.  Test Pattern Generator IP Performance and Resources - Digital ClockThe table shows ALM usage and fMAX for a design with 10 bits per color sample, 2 pixels in parallel, 1 test pattern (digital clock).
Target device ALMs fMAX (MHz)
Agilex™ 7 speed grade 2 (AGFA012R24A2E2V) 1,961 733
Intel Arria 10 speed grade 1 (10AS066H1F34E1HG) 1,721 572
Intel Cyclone 10 GX speed grade 5 (10CX220YF672E5G) 1,723 502
Intel Stratix 10 GX speed grade 1 (1SX280LN2F43E1VG) 2,024 569
Table 829.  Test Pattern Generator IP Performance and Resources - Zone PlateThe table shows ALM usage and fMAX for a design with 10 bits per color sample, 2 pixels in parallel, 1 test pattern (zone plate).
Target device DSP Blocks ALMs fMAX (MHz)
Agilex™ 7 speed grade 2 (AGFA012R24A2E2V) 8 787 804
Intel Arria 10 speed grade 1 (10AS066H1F34E1HG) 8 649 523
Intel Cyclone 10 GX speed grade 5 (10CX220YF672E5G) 8 647 458
Intel Stratix 10 GX speed grade 1 (1SX280LN2F43E1VG) 8 885 651