Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: oxr1660918475177

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

36.2. Interlacer IP Parameters

The IP offers compile-time parameters.
Parameter Values Description
Video data format
Lite mode On or off Turn on for the lite variant of the Intel FPGA Streaming Video protocol
Bits per color sample 8 to 16 Select the number of bits per color sample
Number of color planes 1 to 4 Select the number of color planes per pixel
Number of pixels in parallel 1 to 8 Select the number of pixels in parallel at the input and output interfaces
Interlace settings
Send F1 first On or off Turn on to begin output with an F1 field after any reset to the interlace sequence. If you turn on Memory mapped control interface, you set this behavior via the register map and the parameter is not used.
Override of interlace sequence from image information packet On or off Turn on to allow override of the default interlace sequence if the interlace nibble in the image information packet indicates that the incoming frame was created by deinterlacing original interlaced content (full protocol variant only). If you select Memory mapped control interface, you set this behavior via the register map and the IP does not use this parameter.
Control settings
Memory mapped control interface On or off Turn on for the Avalon memory-mapped control agent interface and to allow run-time configuration via the register map. The Avalon memory-mapped control agent interface is mandatory in lite mode
General
Pipeline ready signals On or off Turn on to add extra pipeline registers to the AXI4-S Tready signals
Debug features On or off Turn on to read back frame information registers (full variants only) and writeable registers via the control agent interface
Separate clock for control interface On or off Turn on to add a separate clock for the control agent interface