Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: eru1618925967528

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

43.1.2. TMO IP Performance and Resource Utilization

Intel provides resource and utilization data for guidance. TMO IP resource utilization depends on the device family and the number of supported bits per sample and pixels in parallel.
Table 805.  Resource Utilization for Agilex™ 7 DevicesTargeting Agilex™ 7 AGIB027R29A1E1V device
Parameters Resource Utilization

Bits per Sample

Pixels in Parallel

ALMs M20Ks DSP Blocks
8 1 7,796 53 56
8 2 11,560 79 105
8 4 18,141 130 203
10 1 7,812 53 56
10 2 11,718 79 105
10 4 18,7979 132 203
12 1 8,034 56 56
12 2 11,881 85 105
12 4 19,998 144 203
Table 806.  Resource Utilization for Intel Arria 10 DevicesTargeting Intel Arria 10 10AS066H1F34E1HG device.
Parameters Resource Utilization

Bits per Sample

Pixels in Parallel

ALMs M20Ks DSP Blocks
8 1 6,396 64 56
8 2 9,051 99 105
8 4 14,330 164 203
10 1 6,536 64 56
10 2 9,287 99 105
10 4 14,787 167 203
12 1 6,628 67 56
12 2 9,569 105 105
12 4 15,249 181 203
Table 807.  Resource Utilization for Intel Cyclone 10 GX DevicesTargeting Intel Cyclone 10 GX 10CX220YF672E5G device
Parameters Resource Utilization

Bits per Sample

Pixels in Parallel

ALMs M20Ks DSP Blocks
8 1 6,437 64 56
8 2 9,076 99 105
10 1 6,539 64 56
10 2 9,313 99 105
12 1 6,662 67 56
12 2 9,543 105 105
Table 808.  Resource Utilization for Intel Stratix 10 DevicesTargeting Intel Stratix 10 1SX280LN2F43E1VG device
Parameters Resource Utilization

Bits per Sample

Pixels in Parallel

ALMs M20Ks DSP Blocks
8 1 7,921 53 56
8 2 11,466 79 105
8 4 18,079 130 203
10 1 8,087 53 56
10 2 11,482 79 105
10 4 18,663 132 203
12 1 8,317 56 56
12 2 12,349 85 105
12 4 18,746 144 203