Visible to Intel only — GUID: qdv1700471597039
Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter IP
8. 1D LUT IP
9. 3D LUT IP
10. Adaptive Noise Reduction IP
11. Advanced Test Pattern Generator IP
12. AXI-Stream Broadcaster IP
13. Bits per Color Sample Adapter IP
14. Black Level Correction IP
15. Black Level Statistics IP
16. Chroma Key IP
17. Chroma Resampler IP
18. Clipper IP
19. Clocked Video Input IP
20. Clocked Video to Full-Raster Converter IP
21. Clocked Video Output IP
22. Color Plane Manager IP
23. Color Space Converter IP
24. Defective Pixel Correction IP
25. Deinterlacer IP
26. Demosaic IP
27. FIR Filter IP
28. Frame Cleaner IP
29. Full-Raster to Clocked Video Converter IP
30. Full-Raster to Streaming Converter IP
31. Genlock Controller IP
32. Generic Crosspoint IP
33. Genlock Signal Router IP
34. Guard Bands IP
35. Histogram Statistics IP
36. Interlacer IP
37. Mixer IP
38. Pixels in Parallel Converter IP
39. Scaler IP
40. Stream Cleaner IP
41. Switch IP
42. Text Box IP
43. Tone Mapping Operator IP
44. Test Pattern Generator IP
45. Unsharp Mask IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO IP
51. Video Timing Generator IP
52. Vignette Correction IP
53. Warp IP
54. White Balance Correction IP
55. White Balance Statistics IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
31.4.3. Setting the VCXO hold over
31.4.4. Restarting the Genlock Controller IP
31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
31.4.7. Disturbing a Reference Clock (a cable pull)
Visible to Intel only — GUID: qdv1700471597039
Ixiasoft
45.3. Unsharp Mask IP Functional Description
The IP creates an unsharp mask by first calculating an approximation to the input image luminance using the input luminance equation:
Equation 11. Input Luminance
The IP then performs a low-pass Gaussian blur (low-pass filter) of .
The IP subtracts this filtered luminance from the original luminance to get the high-frequency components of the luminance.
The IP multiplies this value by the strength to obtain the sharpened luminance. The following equation shows this process.
Equation 12. Sharpened LuminanceThe equation shows that a strength of 0 gives Luma OUT equal to Luma IN .
The IP creates the final output image by calculating a ratio of , which scales the RGB components of the original image. A strength of 0 results in unity ratio.
Equation 13. Final Output Image RGB Scaling
The unsharp mask has an Avalon® memory-mapped agent interface to allow run-time control of the strength of the unsharp mask operation. Set the strength to zero for the IP to pass through the video unchanged.
You need not start the IP via the run-time interface as it starts processing video on its input as soon as it comes out of reset
Changes to the strength run-time control register take effect on the next video line.
Register Behavior
Write values to the control and debugging registers to set video field dimensions. Turn on Debug Features in the GUI so you can read back these values.
Latency
The IP latency under ideal conditions is three video lines plus an additional 34 clock cycles. This latency increases if the streaming video output experiences backpressure via its axi4s_vid_out_tready input. Backpressure increases the latency by the same amount of cycles.
The sharpening strength register setting does not change the latency.