Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: rug1683034483889

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

13.2. Bits per Color Sample Adapter IP Parameters

The IP offers compile-time parameters.
Table 122.  Bits per Color Sample Adapter IP Parameters - BPS Settings
Parameter Allowed range Description
Video data format
Lite mode On or off Turn on to use the lite variant of the Intel FPGA Streaming Video protocol.
Input bits per color sample 8 to 16 Select the number of bits per color sample at the input.
Output bits per color sample 8 to 16 Select the number of bits per color sample at the output.
Number of color planes 1 to 4 Select the number of color planes per pixel
Number of pixels in parallel 1 to 8 Select the number of pixels in parallel.
Control Settings
Memory mapped control interface On or off Turn on for the Avalon memory-mapped agent control interface and to allow runtime configuration via the register map.
General
Pipeline ready signals On or off Turn on to add extra pipeline registers to the AXI4-S tready signals.
Separate clock for control On or off Turn on for a separate clock for the control agent interface.
Debug features On or off Turn on to read back writeable registers via the control agent interface
Table 123.  Bits per Color Sample Adapter IP Parameters - Dithering Settings
Parameter Value Description
Dither Configuration
Enable dithering On or off Turn on for dithering.
Dither Operation

Combined, Subtractive, Additive

Select the type of dither operation

Fixed LFSR seed 1 to (230 -1) Select the 30 MSBs of the 33 bits of the random number generator seed value
Dither Mask
Overwrite noise mask bits On or off -
Blue (Cb) Dither bits 0 to |BPS out - BPS in| Select the number of bits of noise to add to dither for the blue channel (channel 0)
Green (Y) Dither bits 0 to |BPS out - BPS in| Select the number of bits of noise to add to dither for the green channel (channel 1)
Red (Cr) Dither bits 0 to |BPS out - BPS in| Select the number of bits of noise to add to dither for the red channel (channel 2)
Alpha (A) Dither bits 0 to |BPS out - BPS in| Select the number of bits of noise to add to dither for the alpha channel (channel 3)
Figure 26. Dithering Parameters