Visible to Intel only — GUID: emu1640259544590
Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter IP
8. 1D LUT IP
9. 3D LUT IP
10. Adaptive Noise Reduction IP
11. Advanced Test Pattern Generator IP
12. AXI-Stream Broadcaster IP
13. Bits per Color Sample Adapter IP
14. Black Level Correction IP
15. Black Level Statistics IP
16. Chroma Key IP
17. Chroma Resampler IP
18. Clipper IP
19. Clocked Video Input IP
20. Clocked Video to Full-Raster Converter IP
21. Clocked Video Output IP
22. Color Plane Manager IP
23. Color Space Converter IP
24. Defective Pixel Correction IP
25. Deinterlacer IP
26. Demosaic IP
27. FIR Filter IP
28. Frame Cleaner IP
29. Full-Raster to Clocked Video Converter IP
30. Full-Raster to Streaming Converter IP
31. Genlock Controller IP
32. Generic Crosspoint IP
33. Genlock Signal Router IP
34. Guard Bands IP
35. Histogram Statistics IP
36. Interlacer IP
37. Mixer IP
38. Pixels in Parallel Converter IP
39. Scaler IP
40. Stream Cleaner IP
41. Switch IP
42. Text Box IP
43. Tone Mapping Operator IP
44. Test Pattern Generator IP
45. Unsharp Mask IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO IP
51. Video Timing Generator IP
52. Vignette Correction IP
53. Warp IP
54. White Balance Correction IP
55. White Balance Statistics IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
31.4.3. Setting the VCXO hold over
31.4.4. Restarting the Genlock Controller IP
31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
31.4.7. Disturbing a Reference Clock (a cable pull)
Visible to Intel only — GUID: emu1640259544590
Ixiasoft
47.3.1. Video Frame Buffer IP Interfaces
Name | Direction | Width | Description |
---|---|---|---|
Clocks and resets | |||
main_clock_clk | In | 1 | AXI4-S processing clock. |
main_reset_rst | In | 1 | AXI4-S processing reset. |
control_clock_clk | In | 1 | Optional control agent interface clock. |
control_reset_reset | In | 1 | Optional control agent interface reset. |
Control interfaces | |||
av_mm_control_agent_address | In | 7 | Avalon memory-mapped agent address |
av_mm_control_agent_write | In | 1 | Avalon memory-mapped agent write. |
av_mm_control_agent_writedata | In | 32 | Avalon memory-mapped agent write data. |
av_mm_control_agent_byteenable | In | 4 | Avalon memory-mapped agent byte enable. |
av_mm_control_agent_read | In | 1 | Avalon memory-mapped agent read. |
av_mm_control_agent_readdata | Out | 32 | Avalon memory-mapped agent read data. |
av_mm_control_agent_readdatavalid | Out | 1 | Avalon memory-mapped agent read. |
av_mm_control_agent_waitrequest | Out | 1 | Avalon memory-mapped agent wait request. |
Intel FPGA streaming video interfaces | |||
axi4s_vid_in_tdata | In | 141 | AXI4-S data in. |
axi4s_vid_in_tvalid | In | 1 | AXI4-S data valid. |
axi4s_vid_in_tuser[0] | In | 1 | AXI4-S start of video frame. |
axi4s_vid_in_tuser[1] | In | 1 | AXI4-S control or data packet. |
axi4s_vid_in_tuser[N-1:2] | In | 142 | Unused. |
axi4s_vid_in_tlast | In | 1 | AXI4-S end of packet . |
axi4s_vid_in_tready | Out | 1 | AXI4-S data ready. |
axi4s_vid_out_tdata | Out | 141 | AXI4-S data out. |
axi4s_vid_out_tvalid | Out | 1 | AXI4-S data valid. |
axi4s_vid_out_tuser[0] | Out | 1 | AXI4-S start of video frame. |
axi4s_vid_out_tuser[1] | Out | 1 | AXI4-S control or data packet. |
axi4s_vid_out_tuser[N-1:2] | Out | 142 | Unused. |
axi4s_vid_out_tlast | Out | 1 | AXI4-S end of packet . |
axi4s_vid_out_tready | In | 1 | AXI4-S data ready |
Avalon memory-mapped host interfaces Widths for address, data, and burst count buses are as you specify in the GUI. The table shows example widths. |
|||
mem_clock_clk | In | 1 | Optional host interface clock. |
mem_reset_reset | In | 1 | Optional host interface reset. |
av_mm_mem_write_host_address | Out | 32 | Avalon memory-mapped host address |
av_mm_mem_write_host_write | Out | 1 | Avalon memory-mapped host write. |
av_mm_mem_write_host_burstcount | Out | 5 | Avalon memory-mapped host write burst count. |
av_mm_mem_write_host_writedata | Out | 64 | Avalon memory-mapped host write data. |
av_mm_mem_write_host_waitrequest | In | 1 | Avalon memory-mapped host wait request. |
av_mm_mem_read_host_address | Out | 32 | Avalon memory-mapped host address |
av_mm_mem_read_host_read | Out | 1 | Avalon memory-mapped host read. |
av_mm_mem_read_host_burstcount | Out | 5 | Avalon memory-mapped host read burst count. |
av_mm_mem_read_host_readdata | In | 64 | Avalon memory-mapped host read data. |
av_mm_mem_read_host_readdatavalid | In | 1 | Avalon memory-mapped host read data valid. |
av_mm_mem_read_host_waitrequest | In | 1 | Avalon memory-mapped host wait request. |
Related Information
141
The equation gives all tdata widths sizes in these interfaces:
max(2, ceil ((bits per color sample × number of color planes)/8)) × pixels in parallel × 8
142
This equation gives all tuser widths sizes in these interfaces N = ceil (tdata width / 8)