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Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter IP
8. 1D LUT IP
9. 3D LUT IP
10. Adaptive Noise Reduction IP
11. Advanced Test Pattern Generator IP
12. AXI-Stream Broadcaster IP
13. Bits per Color Sample Adapter IP
14. Black Level Correction IP
15. Black Level Statistics IP
16. Chroma Key IP
17. Chroma Resampler IP
18. Clipper IP
19. Clocked Video Input IP
20. Clocked Video to Full-Raster Converter IP
21. Clocked Video Output IP
22. Color Plane Manager IP
23. Color Space Converter IP
24. Defective Pixel Correction IP
25. Deinterlacer IP
26. Demosaic IP
27. FIR Filter IP
28. Frame Cleaner IP
29. Full-Raster to Clocked Video Converter IP
30. Full-Raster to Streaming Converter IP
31. Genlock Controller IP
32. Generic Crosspoint IP
33. Genlock Signal Router IP
34. Guard Bands IP
35. Histogram Statistics IP
36. Interlacer IP
37. Mixer IP
38. Pixels in Parallel Converter IP
39. Scaler IP
40. Stream Cleaner IP
41. Switch IP
42. Text Box IP
43. Tone Mapping Operator IP
44. Test Pattern Generator IP
45. Unsharp Mask IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO IP
51. Video Timing Generator IP
52. Vignette Correction IP
53. Warp IP
54. White Balance Correction IP
55. White Balance Statistics IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
31.4.3. Setting the VCXO hold over
31.4.4. Restarting the Genlock Controller IP
31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
31.4.7. Disturbing a Reference Clock (a cable pull)
Visible to Intel only — GUID: tai1655476695213
Ixiasoft
33.2. Genlock Signal Router IP Parameters
The IP offers compile-time parameters.
| Parameter | Values | Description |
|---|---|---|
| Build configuration | ||
| Length of clock pulse | 1 to 32 | The number of clocks for the output genlock pulse |
| Number of genlock inputs | 1 to 32 | The number of input ports |
| Number of genlock outputs | 1 to 32 | The number of output ports |
| General-purpose input conduit | True or false | Turn on a general-purpose input port for this IP |
| Number of bits of GPI | 1 to 32 | The number of bits for the general-purpose input interface |
| General-purpose output conduit | True or false | Turn on a general-purpose output port for this IP |
| Number of bits of GPO | 1 to 32 | The number of bits for the general-purpose output interface |
| Genlock output type | Discrete timing signals, Clocks only | Select the type for all available outputs |
| Genlock Input Type: AXI-S FR (Per Input Interface) | ||
| Number of bits per color plane | 8 to 16 | The number of bits per color sample at the input |
| Number of pixels in parallel | 1 to 8 | The number of pixels transmitted every clock cycle. |
| Number of color planes | 1 to 4 | The number of color planes per pixel |
| AXI4-S FR interface TREADY | True or false | Enable the TREADY signal as part of the full-raster interface |
| Genlock Input Type: Discrete timing Clocked Video signals (Per Input Interface) | ||
| Clock | 0 to 1 | Discrete input interface has Input clock signal |
| F | 0 to 1 | Discrete input interface has Input field signal |
| V | 0 to 1 | Discrete input interface has Input vertical blanking signal |
| H | 0 to 1 | Discrete input interface has Input horizontal blanking signal |
| V sync | 0 to 1 | Discrete input interface has Input vertical sync signal |
| H sync | 0 to 1 | Discrete input interface has Input horizontal sync signal |
| Toggle | 0 to 1 | Discrete input interface has Input field pulse signal |
| Pulse | 0 to 1 | Discrete input interface has Input field toggle signal |
Figure 100. Genlock Signal Router IP GUI
