Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

14.3. Black Level Correction IP Functional Description

The Black Level Correction IP removes the pedestal offset value from the input video stream and resizes the result back to the full dynamic range of the video stream. You write pedestal and scaler values for each of the 4 color channels of the 2x2 color filter array over the external processor interface. The IP uses these values to calculate the output video stream. The IP supports arbitrary 2x2 color filter arrays.
Figure 34. Black Level Correction IP Block Diagram

The pedestal remover subtracts the offset values from the input pixel values. The IP clips negative values to zero if you turn off Reflect around zero, or if you turn on Reflect around zero but set the run-time CONTROL register Clip Zero En bit to turn on clipping to zero. The IP reflects the negative values around zero if you turn on Reflect around zero and clear the run-time CONTROL register Clip Zero En bit to turn off clipping at zero.

Figure 35. The effect of reflection around zero

The scaler part of the IP multiplies the intermediate result after subtraction with an arbitrary factor that you program over the external processor interface. You must calculate the correct multiplication factor from the dynamic range of the video stream and the pedestal value. The IP clips the overflowed values to the maximum value of the output video stream.

You must set the color filter array phase to its correct value, which depends on the framing, rotation, and flipping options you apply on the original image that an imaging sensor captures. If you do not set the correct color filter array phase, the IP may mix color channels and produce incorrect outputs.

Figure 36. Examples of 2x2 Color Filter Arrays For a 6x6 section of an image