Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: gvz1618926059132

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

43.3. TMO IP Block Description

The IP accepts RGB-format video input as an Intel FPGA video streaming interface, statistically analyses image content (locally and globally), and dynamically enhances the luma range to improve overall image contrast. This IP enhances input video frame imagery into a well-lit and detailed image.
Figure 120. TMO IP High-level block diagram.

The TMO IP consists of several blocks for video processing, memory, and control. The video datapath includes a luma extractor, image statistics calculator, a soft-processor-based mapping LUT generator, CPU register interface, a contrast enhancement engine, and an image enhancer.

The luma extractor takes an RGB input frame, analyzes it, and extracts luminance. The image statistics calculator takes luma information contained in a video frame and provides a set of global and local statistic parameters regarding the contrast information on the input video frame.

The IP collects local information about the input images in different regions on a video frame, providing the necessary granularity to properly enhance contrast in areas within the video frame that need to be adjusted.

The soft-processor-based mapping LUT generator takes the data gathered from the image statistics calculator block and generates a set of mapping transfer functions. The IP temporarily stores the mapping transfer functions in LUTs to reduce resource utilization footprint.

The contrast enhancement engine applies different amounts of mapping transfer functions in different regions of a video frame, providing the necessary granularity to properly enhance contrast in areas within the frame that you need to adjust. The TMO IP does not use external video frame buffers. Consequently, the contrast enhancement process that the IP applies to the current frame uses statistical information it collects from the previous video frame.

The image enhancer takes the image statics information gathered from the input video frame and with the generated mapping transfer function, it enhances the luma range. The image enhancer calculates a set of weights that it applies to the input RGB data to generate contrast enhanced RGB output video streams.

The embedded Nios® V/g processor used as a mapping LUT generator, is packaged as part of the TMO IP, and customers do not have direct access to it. An external Avalon memory-mapped processor control interface allows you to interact and configure TMO IP, giving them access to the control registers. Because of a higher level of abstraction, a set of software APIs allow you to easily configure and interact with the IP.

You need to get the free license for the Nios V processor to compile the design in Intel Quartus Prime software.

Figure 121.  Graphical description of a tile-based histogram generationThe figure shows a graphical description of the tile-based approach, explicitly showing tiles boundaries. Tile boundaries are not visible when you operate the TMO IP. The figure shows them only to demonstrate the IP operation.