Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: zos1708080383143

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

22.1.1. Color Plane Manager IP Performance and Resources

Intel provides resource and utilization data for guidance. The IP resource utilization depends on the device family and the number of supported bits per color sample, colors per pixel, and pixels in parallel.
Table 351.  Color Plane Manager Performance and Resources – rearrange modeThe table shows ALM usage and fMAX for a design with a color plane manager IP in rearrange mode with 2 pixels in parallel, 10 bits per color sample with 3 color planes input and output with memory-mapped control.
Target Device Maximum Frame Size ALMs fMAX (MHz)

Intel Agilex 7 speed grade 2 (AGFA012R24A2E2V)

4K 344 981

Intel Cyclone 10 GX speed grade 5 (10CX220YF672E5G)

1080p 272 645
Table 352.  Color Plane Manager Performance and Resources – merge modeThe table shows ALM usage and fMAX for a design with a color plane manager in merge mode with 2 pixels in parallel, 10 bits per color sample with 3 color planes input and output, and input 1 aux/user packets removed.
Target Device Maximum frame Size ALMs fMAX (MHz)

Intel Agilex speed grade 2 (AGFA012R24A2E2V)

4K 448 862

Intel Cyclone 10 GX speed grade 5 (10CX220YF672E5G)

1080p 360 645
Table 353.  Color Plane Manager Performance and Resources – split mode

The table shows ALM usage and fMAX for a design with a color plane manager in split mode with 2 pixels in parallel, 10 bits per color sample with 3 color planes input and output, and output 1 aux/user packets removed.

Target Device Maximum Frame Size ALMs fMAX (MHz)

Intel Agilex 7 speed grade 2 (AGFA012R24A2E2V)

4K 555 975

Intel Cyclone 10 GX speed grade 5 (10CX220YF672E5G)

1080p 494 645