Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: qwc1703079283495

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

52.1.1. Vignette Correction IP Performance and Resources

Intel provides resource and utilization data for guidance only. The IP resource utilization depends on the device family, compilation tool version, compilation seed randomization, and other parameters.
Table 1064.  Vignette Correction IP Performance and ResourcesWith Independent color plane correction mesh gain coefficients on
Device Pixel in Parallel Bits per Color Sample Max Resolution CFA Enable ALM M20k DSP

fMAX

(MHz)

Intel Agilex 7 speed grade 2 (AGFA012R24A2E2V) 1 10 2048 On 1404 9 7 750
1 10 2048 Off 2329 7 21 723
4 16 8192 On 3419 9 28 716
4 16 8192 Off 7692 7 84 613
Intel Arria 10 speed grade 1 (10AS066H1F34E1HG) 1 10 2048 On 1139 14 7 524
1 10 2048 Off 1656 19 21 495
2 10 4096 On 1600 19 14 518
2 10 4096 Off 2793 31 42 510
Intel Cyclone 10 GX speed grade 5 (10CX220YF672E5G) 1 10 2048 On 1133 14 7 472
1 10 2048 Off 1657 19 21 440
Intel Stratix 10 speed grade 1 (1SX280LN2F43E1VG) 1 10 2048 On 1426 9 7 583
1 10 2048 Off 2373 7 21 525
2 10 4096 On 2129 9 14 565
2 10 4096 Off 4225 7 42 535