Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: ptq1619516629947

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

53.2. Warp IP Parameters

The IP offers various compile-time parameters.
Table 1105.  Warp IP Parameters
Parameter Values Description
Video data format
Lite mode On The IP only operates in Lite mode, with no support for control packets.
Number of pixels in parallel 1, 2, 4, or 8 Number of pixels processed in parallel. When Use easy warp is on, the IP supports only 1 or 2 pixels in parallel.
Number of color planes 3 Number of color planes per pixel.
Bits per color sample 10 Number of bits per color sample
Maximum input video width 2048, 3840, 4096, or 7680. Maximum number of pixels per input line. Configures the depth of line buffers in the video input block.

The IP can process image widths of up to 7680. When Use easy warp is on, the maximum video width is limited to 2048 or 3840.

Maximum output video width 2048, 3840, 4096, or 7680. Maximum number of pixels per output line. Configures the depth of line buffers in the video output block. When Use easy warp is on, the maximum video width is limited to 2048 or 3840.
Configuration Settings
Use easy warp On or off

Turn on for a limited set of warp operations. Turn off for arbitrary warps.

The IP can only process image heights and widths that are a multiple of two when you select 2 pixels in parallel and turn on Use easy warp.

Memory frame buffer size SD, HD, UHD, or 8K

The amount of memory space the IP allocates to each frame buffer.

Each pixel is 4 bytes in size.

  • SD is 1024x1024 pixels
  • HD is 2048x2048 pixels
  • UHD is 4096x4096 pixels
  • 8K is 8192x8192 pixels
Enable Debug Registers On or off Turn on to read back various registers containing debugging information.

Engine Configuration Settings

(These parameters are only available when Use easy warp is off)

Number of engines 1, 2 or, 4 Number of processing engines to use. Each engine processes one pixel per clock cycle.
Use mipmaps On or off When you turn on Use mipmaps, the IP uses a pyramid of automatically downscaled mipmap images to support arbitrary warps with downscaled regions up to 256:1. When you turn off Use mipmaps, arbitrary warps are limited to downscaled regions up to 2:1.

When Number of pixels in parallel is 1 or 2, the IP does not support turning on Use mipmaps with a Memory frame buffer size of 8K

Use single memory bounce On or off

Defines how the engines are connected to and use the external memory. When you turn off Use single memory bounce the engines both read and write their video data through the memory (double memory bounce). When you turn on Use single memory bounce the engines only read video data from memory and their output data passes directly to the video output process of the warp IP.

The IP can only generate image heights that are a multiple of 8 lines when you turn on Use single memory bounce.

Cache blocks per engine 256, 512 or 1024 Only available when Use single memory bounce is on. Defines the amount of cache memory that is available to each engine. The amount of cache memory required is a function of the input resolution the IP processes, the required warp and the number of engines you select.
Figure 142. Warp IP GUIWhen Use easy warp is on, ensure that both Use mipmaps and Use single memory bounce are off.
Table 1106.  Warp IP throughput for different parameters
Number of pixels in parallel The number of processing engines to use fMAX (MHz) Performance
1 1 150 Image resolutions of up to 1920x1080 at 60 fps.
1 1 300 Image resolutions of up to 3840x2160 at 30 fps.
2 2 300 Image resolutions of up to 3840x2160 at 60 fps.
1 1 600
4 4 600 Image resolutions of up to 3840x2160 at 120 fps or 7680x4320 at 30 fps.