Visible to Intel only — GUID: vja1683034446217
Ixiasoft
Visible to Intel only — GUID: vja1683034446217
Ixiasoft
13.1. About the Bits per Color Sample Adapter IP
When the input bits per color sample is less than the output bits per color sample, the IP adds the required number of bits at the LSB end of the tdata bus. The IP fixes these additional bits to 0. When the input bits per color sample is greater than the output bits per color sample, the IP clips the required number of bits from the LSB end of each color sample.
When you configure the IP for use with the lite variant of the Intel FPGA Streaming Video interface protocol, it consumes no FPGA resources as the clip and pad operations do not require any. However, when you configure the IP for use with the full variant of the protocol, a small amount of additional logic is required to ensure that the clip and pad operations do not affect the data in the nonvideo packets. The full variant of the protocol includes image information packets, and these packets contain a field indicating how many of the bits in each color plane are active for the current video stream.
When using the full variant of the protocol, you can include an Avalon Memory-mapped agent control interface to control the output bits per color field value at runtime via the register map. If you do not turn on Memory mapped control interface, the IP uses the default value for the bits per color field. When converting from a lower input bits per color sample value at the input to a higher value at the output, the IP does not modify this field as the pixel data does not change. However, when converting from a higher input bits per color sample value to a lower output bits per color sample value, you must modify the active bits per color sample field if it indicates a value greater than the maximum bits per color supported at the output.
