Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

31.1. About the Genlock Controller IP

The Genlock Controller IP is a control loop system that matches the frequency of the voltage-controlled crystal oscillator (VCXO) clock to the selected reference clock.

You can use the IP in an FPGA to support external voltage-controlled crystal oscillator (VCXO) clock tracking to a reference clock. The IP is highly parameterizable and programmable for various scenarios.

Typically, you generate video receiver and transmitter pixel clocks and video processing clock from three different clock generators. Hence, they are asynchronous. If the video receiver and transmitter clocks are asynchronous, the output video stream drifts over time relative to the input video stream.

The Genlock Controller IP allows locking receiver and transmitter pixel clocks, to avoid any drifting or rolling effect on the output video stream. The video drifting is visually noticeable when the processing video pipeline does not include a frame buffer in it.

Figure 95. Video Processing Pipeline

The figure shows a video processing pipeline without frame buffer. It shows how adding a genlock to the input and output video affects the output video.