1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter IP
8. 1D LUT IP
9. 3D LUT IP
10. Adaptive Noise Reduction IP
11. Advanced Test Pattern Generator IP
12. AXI-Stream Broadcaster IP
13. Bits per Color Sample Adapter IP
14. Black Level Correction IP
15. Black Level Statistics IP
16. Chroma Key IP
17. Chroma Resampler IP
18. Clipper IP
19. Clocked Video Input IP
20. Clocked Video to Full-Raster Converter IP
21. Clocked Video Output IP
22. Color Plane Manager IP
23. Color Space Converter IP
24. Defective Pixel Correction IP
25. Deinterlacer IP
26. Demosaic IP
27. FIR Filter IP
28. Frame Cleaner IP
29. Full-Raster to Clocked Video Converter IP
30. Full-Raster to Streaming Converter IP
31. Genlock Controller IP
32. Generic Crosspoint IP
33. Genlock Signal Router IP
34. Guard Bands IP
35. Histogram Statistics IP
36. Interlacer IP
37. Mixer IP
38. Pixels in Parallel Converter IP
39. Scaler IP
40. Stream Cleaner IP
41. Switch IP
42. Text Box IP
43. Tone Mapping Operator IP
44. Test Pattern Generator IP
45. Unsharp Mask IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO IP
51. Video Timing Generator IP
52. Vignette Correction IP
53. Warp IP
54. White Balance Correction IP
55. White Balance Statistics IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
31.4.3. Setting the VCXO hold over
31.4.4. Restarting the Genlock Controller IP
31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
31.4.7. Disturbing a Reference Clock (a cable pull)
31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
Locking to an external reference clock involves various bits within the same register. You require multiple writes to control the behavior in the correct sequence and to also ensure that any transition pulses are wide enough.
- Always disable the PFD (in case the IP previously uses them):
- Disable LPF
- Write LPF Control 1 Register = 0x0
- Write LPF Control 3 Register = 0x0
- Disable PFD
- Write PFD Control Register = 0x0
- Write TxRx VCXO Clock Ratio Register = 0x0
- Write TxRx Reference Clock Ratio Registers = 0x0
- Disable LPF
- Setup and enable the LPF, which you can do as the PFD is still disabled that feeds the LPF:
- Initialize LPF. In this Phase Mode example, the Integrator reset value = 0, P and I gain are 3.0 and 1.0 respectively. D is not used, nor is negative gain or I fraction gain mode. Lock status is Phase mode and shift the LSB position by 1 (for checking lock). Also reset DAC Saturation bit, in case it is set (bit 29, which you need to clear).
- Write LPF Control 2 Register = 0x0
- Write LPF Control 1 Register = 0x600d0000
- Write LPF Control 3 Register = 0x000301
- Initialize LPF. In this Phase Mode example, the Integrator reset value = 0, P and I gain are 3.0 and 1.0 respectively. D is not used, nor is negative gain or I fraction gain mode. Lock status is Phase mode and shift the LSB position by 1 (for checking lock). Also reset DAC Saturation bit, in case it is set (bit 29, which you need to clear).
- Perform the enable as an extra step (maintain all the other bits, except bit 29, which you should return to ‘0’):
- Enable the LPF
- Read modify write bit 0 LPF control 1 register = 0x400d0001
- Enable the LPF
- Setup and enable the PFD by setting the output update period MSBs, the choice of reference clock, its rate, and place the reference clock and VCXO clock in reset in one operation:
- Initialize the PFD. In this example, set 10 bits. Set the 10 LSBs to ‘1’ and the upper 6 MSBs to ‘0’. The 16 MSBs multiply the build time value by 1024.
- Write bits 31:16 PFD Control Register = 0x03ff
- In this example choose Ref0 and VCXO clock ratios to be 1:1. They both have theoretically the same frequency value:
- Write TxRx VCXO clock ratio register = 0x04000000
- Write TxRx reference clock ratio registers = 0x04000000
- Initialize the PFD (reset reference and VCXO clock counters)
- Write bits 7:4 for the selected clock counter (bit 4 in our example) and bit 12 for VCXO clock counter PFD control register (Reg 0) = 1
- Initialize the PFD. In this example, set 10 bits. Set the 10 LSBs to ‘1’ and the upper 6 MSBs to ‘0’. The 16 MSBs multiply the build time value by 1024.
- Take the internal clock counters out of reset:
- Read modify write bits 7:4 for the selected clock counter (bit 4 in the example) and bit 12 for VCXO clock counter PFD control register (Reg 0) = 0.
- Enable the PFD:
Read modify write bit 0 PFD control register (Reg 0) = 0x1
- Write the LPF value to drive DAC:
- Write DAC control register (Reg 5) = 0x3