Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: ytc1723713231527

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

42.3.3. Text Box IP Interfaces

Table 776.  Text Box IP Interfaces
Name Direction Width Description
Clocks and Resets
main_clock_clk In 1 AXI4-S video processing clock
main_reset_rst In 1 AXI4-S video processing reset
agent_clock_clk In 1 Control agent interface clock
agent_reset_rst In 1 Control agent interface reset
Control interfaces
av_mm_control_agent_address In 131 Avalon memory-mapped agent address
av_mm_control_agent_write In 1 Avalon memory-mapped agent write
av_mm_control_agent_writedata In 32 Avalon memory-mapped agent write data
av_mm_control_agent_byteenable In 4 Avalon memory-mapped agent byte enable
av_mm_control_agent_read In 1 Avalon memory-mapped agent read
av_mm_control_agent_readdata Out 32 Avalon memory-mapped agent read data
av_mm_control_agent_readdatavalid Out 1 Avalon memory-mapped agent read data valid
av_mm_control_agent_waitrequest Out 1 Avalon memory-mapped agent wait request
irq Out 1 Interrupt sender
Intel FPGA streaming video interfaces
axi4s_vid_out_tdata Out 132 AXI4-S data out
axi4s_vid_out_tvalid Out 1 AXI4-S data valid
axi4s_vid_out_tuser Out 133 AXI4-S user
axi4s_vid_out_tlast Out 1 AXI4-S end of packet
axi4s_vid_out_tready In 1 AXI4-S data ready
131 log2(128 + ((number of characters per line * number of lines)/4))
132 max(2, ceil((bits per color sample × number of color planes)/8)) × pixels in parallel
133 ceil(tdata width / 8)