Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: fhl1638963472971

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

34.1. About the Guard Bands IP

The IP compares each color plane in the input video to upper and lower guard band values. If the value in any color plane exceeds the upper guard band, the IP replaces the value with the upper guard band. Similarly, if the value in any color plane falls below the lower guard band, the IP replaces the value with the lower guard band.

You can specify different guard band values for each color plane. You can alter these values at run-time through the Avalon memory-mapped interface. Otherwise, the guard band values are fixed at compile-time.

The input can be unsigned data or signed 2’s complement data for which the IP converts the data to an unsigned format (by adding half the maximum range) before applying guard bands. The guard bands are specified as unsigned values.

The IP can drive the output data as signed data but, as with signed input data, the IP applies guard bands on the unsigned data before it converts it to signed output. The IP converts the output data to a signed format by subtracting half the maximum range after applying guard bands.

You cannot select both signed input and signed output data. The IP prepares data for other video and vision processing IPs, which primarily operate on unsigned data. You can place this IP before and after another video and vision IP, configuring the first for signed input and the second to use signed output data.