Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

19.1. About the Clocked Video Input IP

The Clocked Video Input IP allows transferring video data between a timing-aware clocked video input interface and a timing-agnostic video streaming output interface. The IP provides a seamless conversion by removing video timing data from a full-raster bus and leaves just the pixel data in Intel FPGA streaming video format. Typically, the IP is a bridge to transfer data from video connectivity to video processing IP.
The IP accepts full-raster video input format as a full-raster interface of pixel data and timing markers embedded in the TDATA bus of an AXI4-S interface. Also, the IP filters out the timing markers from the TDATA bus and provides a video-active only data format on the output interfaces that conforms to the Intel FPGA streaming video protocol specification.
Figure 44. Clocked Video Input IP Block Diagram

The IP provides a wide variety of video statistic collection, e.g. frame counter, frame per second, active and blanking video frame information. All this information is accessible directly from a processor register interface.

Figure 45. Video Statistics Information

The figure provides an example of the video statistics information that the IP can provide for a 1080p60 video resolution.

By default, the IP only provides full-raster and video active high and width information as part of the video statistic collection. However, if you select the video telemetrics information in the GUI, the IP provides a more comprehensive set of video timing parameters. An optional frame per second counter provides you with an accurate frame rate estimation and its corresponding full-raster video clock.

The IP provides autopolarity detection for the horizontal and vertical timing markers, Vsynch and Hsynch, and allows automatic detection of interlaced video formats. You can configure automatic detection using the processor control interface.

Figure 46. Full-Raster TimingThe figure shows how the video statistics values collected by the IP correlate with a full-raster video frame.

The IP also provides an asynchronous FIFO buffer to handle the clock domain jump from input to output video domain. An optional frame cleaner is available at the back end of the IP. The frame cleaner allows you to automatically pad an incomplete frame (for example, because of an unplugged cable) by inserting a user configurable color pattern. You can turn on or off the frame cleaner at run time using the processor control interface.

Figure 47. Corrupted FrameThe figure shows an example where an output frame is corrupted, and the embedded frame cleaner adds padding (pink pixels) from the Clocked Video Input IP to complete the video output raster.

The IP only supports lite variants. For more information about full and lite variants, refer to the Intel FPGA Streaming Video Protocol Specification