Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: ayo1650978175404

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

25.1. About the Deinterlacer IP

The IP takes a stream of interlaced video fields and outputs progressive frames generated using a bob, weave, or motion adaptive algorithm. The IP passes progressive video frames through unchanged.

The bob algorithm produces output frames by filling in the missing lines from the current field with the linear interpolation of the lines above and below. The deinterlacing algorithm can be setup for:

  • Deinterlacing F0 fields while dropping F1 fields
  • Deinterlacing F1 fields while dropping F0 fields
  • Deinterlacing both F0 and F1 fields

For the bob deinterlacer, with a regular input sequence of alternating field types, the frame rate on the output matches the input field rate when deinterlacing both F0 and F1 fields. Otherwise the IP halves the field rate.

The weave algorithm creates an output frame by filling all the missing lines in the current field with lines from the previous field. With a regular input sequence of alternating field types, the IP halves the field rate. The weave deinterlacer includes an optional FIFO buffer with fixed depth 1024.

The motion adaptive algorithm avoids the weaknesses of bob and weave algorithms by using bob deinterlacing for moving areas of the image and weave deinterlacing for still areas. The frame rate on the output matches the input field rate when deinterlacing both F0 and F1 fields.

The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. For full variants, the deinterlacer IP decodes input resolutions and field type by reading image information packets. Lite variants use the register interface to determine input resolutions and whether the video is progressive or interlaced. Lite variants then decode the axi4s_vid_in_tuser[1] signal to determine the incoming field's interlaced type. If you require high quality motion adaptive deinterlacing, use protocol converters and the video and image processing suite deinterlacer II IP.