Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

32.4. Generic Crosspoint IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 575.  Generic Crosspoint IP Registers
Offset Register Access
Parameterization Registers
0x000 VID_PID RO
0x004 VERSION_NUMBER RO
0x008 NUM_INPUTS RO
0x00C NUM_OUTPUTS RO
Core Specific Registers
0x140 REG_OUTPUT_0 RW
0x144 REG_OUTPUT_1 RW
0x148 REG_OUTPUT_2 RW
0x14C REG_OUTPUT_3 RW
0x150 REG_OUTPUT_4 RW
0x154 REG_OUTPUT_5 RW
0x158 REG_OUTPUT_6 RW
0x15C REG_OUTPUT_7 RW
0x160 REG_OUTPUT_8 RW
0x164 REG_OUTPUT_9 RW
0x168 REG_OUTPUT_10 RW
0x16C REG_OUTPUT_11 RW
0x170 REG_OUTPUT_12 RW
0x174 REG_OUTPUT_13 RW
0x178 REG_OUTPUT_14 RW
0x17C REG_OUTPUT_15 RW
0x180 REG_OUTPUT_16 RW
0x184 REG_OUTPUT_17 RW
0x188 REG_OUTPUT_18 RW
0x18C REG_OUTPUT_19 RW
0x190 REG_OUTPUT_20 RW
0x194 REG_OUTPUT_21 RW
0x198 REG_OUTPUT_22 RW
0x19C REG_OUTPUT_23 RW
0x1A0 REG_OUTPUT_24 RW
0x1A4 REG_OUTPUT_25 RW
0x1A8 REG_OUTPUT_26 RW
0x1AC REG_OUTPUT_27 RW
0x1B0 REG_OUTPUT_28 RW
0x1B4 REG_OUTPUT_29 RW
0x1B8 REG_OUTPUT_30 RW
0x1BC REG_OUTPUT_31 RW

Register Bit Descriptions

Table 576.  Vid_pid
Bits Description
31:0 Product Identification Number
Table 577.  Version_number_pid
Bits Description
31:0 IP Version Number
Table 578.  Reg_output_N where N goes from 0 to 31
Bits Description
31:0 Number of the input port to select