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1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter IP
8. 1D LUT IP
9. 3D LUT IP
10. Adaptive Noise Reduction IP
11. Advanced Test Pattern Generator IP
12. AXI-Stream Broadcaster IP
13. Bits per Color Sample Adapter IP
14. Black Level Correction IP
15. Black Level Statistics IP
16. Chroma Key IP
17. Chroma Resampler IP
18. Clipper IP
19. Clocked Video Input IP
20. Clocked Video to Full-Raster Converter IP
21. Clocked Video Output IP
22. Color Plane Manager IP
23. Color Space Converter IP
24. Defective Pixel Correction IP
25. Deinterlacer IP
26. Demosaic IP
27. FIR Filter IP
28. Frame Cleaner IP
29. Full-Raster to Clocked Video Converter IP
30. Full-Raster to Streaming Converter IP
31. Genlock Controller IP
32. Generic Crosspoint IP
33. Genlock Signal Router IP
34. Guard Bands IP
35. Histogram Statistics IP
36. Interlacer IP
37. Mixer IP
38. Pixels in Parallel Converter IP
39. Scaler IP
40. Stream Cleaner IP
41. Switch IP
42. Text Box IP
43. Tone Mapping Operator IP
44. Test Pattern Generator IP
45. Unsharp Mask IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO IP
51. Video Timing Generator IP
52. Vignette Correction IP
53. Warp IP
54. White Balance Correction IP
55. White Balance Statistics IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
31.4.3. Setting the VCXO hold over
31.4.4. Restarting the Genlock Controller IP
31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
31.4.7. Disturbing a Reference Clock (a cable pull)
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9.3.1. 3D LUT IP Interfaces
The IP has three functional interfaces.
The interfaces are:
- Intel FPGA video stream input interface
- Intel FPGA video stream output interface
- Avalon Memory-Mapped compatible CPU interface
The 3D LUT IP control interface uses Avalon Memory-Mapped protocol to access control and RAM interface registers.
Clocks
The 3D LUT IP has two clock domains, each with a corresponding reset signal.
| Clock name | Description |
|---|---|
| cpu_clock | CPU interface clock domain |
| vid_clock | Video processing clock domain |
The CPU interface uses little bandwidth and therefore does not impose a minimum clock frequency. The video clock frequency depends on the video resolution, frame rate, and the 3D LUT IP’s number of pixels in parallel. For example, a 300 MHz clock at 2 pixels in parallel supports active video resolutions up to 4096x2160 at 60 Hz.
All RTL-based blocks that transfer or receive data from a different clock domain include clock domain crossing (CDC) circuits for both, single bit and data bus signal cases. The CDC safely allows exchange of data between the two asynchronous clock domains. This principle applies to the control signals from the CPU interface to the main video datapath. The 3D LUT IP includes a .sdc file to constrain this CDC.
Resets
| Reset name | Description |
|---|---|
| cpu_reset | CPU interface clock domain reset. |
| vid_reset | Video processing clock domain reset. |
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