Visible to Intel only — GUID: eet1725280817149
Ixiasoft
Visible to Intel only — GUID: eet1725280817149
Ixiasoft
13.3. Bits per Color Sample Adapter IP Dithering Functional Description
Dithering Upwards
The IP processes the dithering upwards after shifting the value to the desired output BPS.
Dithering Downwards
The IP processes the dithering upwards before shifting the value to the desired output BPS.
Fixed LSFR Seed Value
Linear feedback shift registers (LSFR) generate pseudo-random numbers for the noise. For the largest screen without creating a repeating pattern, a minimum size of 32 shift registers is required. The IP implements a size of 33 shift registers to reduce number of taps required and increases the maximum frequency of the LFSR. The Fibonacci LFSR has tap points at bit 0 and bit 13.
The IP gets the noise bits by masking the random number generated such that only the number of bits required shows. The MSB of the number generated then determines the operation (addition or subtraction).
The number of masking bits is the sum of mask for each individual color plane. The IP packs it in the order of the color plane number (i.e. first few bits is for color plane 0 and color plane 1, etc.). The IP uses this packing order for the sign bits. The IP interprets the sign bits as if you assert it as additive, otherwise it is subtractive. The LFSR value is reset to the value in the Fixed LSFR Seed.
The Fixed LSFR Seed value that you select is the most significant 30-bits. The least significant 3-bit remainder is determined by the pixel-in-parallel number. The pixel in parallel calculation is then more efficient as it does not require and adder to calculate the PIP seed.