HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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5.1.26. TX AXI4-Stream Auxiliary Packetizer

This block converts auxiliary data from the AXI4-stream format to Avalon streaming format to be accepted by the auxiliary data port of the HDMI TX core. It also provides safe clock crossing of data from the CPU clock domain.

Input AXI4-stream data follows the protocol described in Auxiliary AXI4-stream protocol transfer example. Output data is Avalon-streaming data, follows the format shown in Auxiliary Packet Encoder Input Figure.

Throughout the transfer of each data packet aux_valid must remain high. Therefore, data output must not commence until this block receives a complete data packet.

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