HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.1. Terms and Acronyms

Table 1.  Acronyms
Acronym Definition
AI Audio InfoFrame
AM Audio Metadata
AVI Auxiliary Video Information
AXI2CV AXI4-Stream to Clocked Video Converter
BPC Bit Per Component
CEC Consumer Electronics Control
CV2AXI Clocked Video to AXI4-Stream Converter
DDC Display Data Channel
DVI Digital Visual Interface
EDID Extended Display Identification Data
FFE Feed forward error
FRL Fixed Rate Link
GCP General Control Packet
HPD Hotplug Detect
LPCM Linear Pulse Code Modulation
LTS Link Training State
RO Read Only Access
RW Read and Write Access
SCDC Status and Control Data Channel
TERC4 TMDS Error Reducion Coding - 4 bit
TMDS Transision Minimized Differential Signaling
VESA Video Electronics Standards Association
VSI Vendor Specific InfoFrame
W1C Write 1 to Clear the register bit

Did you find the information on this page useful?

Characters remaining:

Feedback Message