HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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9.2.2.21. VIDEO_MODE_VALID (0x6D)

Table 120.  VIDEO_MODE_VALID (0x6D)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Video mode valid 0 RW
  • Set to 0 before programming the video mode registers (0x54-0x64).
  • Set to 1 to indicate that the video mode registers (0x54-0x64) programmed are valid and can be used for video output.
0x0

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