HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022

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Document Table of Contents VSI_CONTROL (0x0D)

Table 74.  VSI_CONTROL (0x0D)
Name Bit(s) Access Description Reset
reserved 31:1 - - -
VSI disable 0 RW When set to 1, HDMI TX core does not send VSI infoframes from the VSI_PACKET registers.

When set to 0, HDMI TX core sends VSI infoframes from the VSI_PACKET registers


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