HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9.1.1.10. VSI_CONTROL (0x0D)

Table 74.  VSI_CONTROL (0x0D)
Name Bit(s) Access Description Reset
reserved 31:1 - - -
VSI disable 0 RW When set to 1, HDMI TX core does not send VSI infoframes from the VSI_PACKET registers.

When set to 0, HDMI TX core sends VSI infoframes from the VSI_PACKET registers

0x0

Did you find the information on this page useful?

Characters remaining:

Feedback Message