HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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9.3.1.13. USER_BUFFER_LEVEL (0x12)

Table 131.  USER_BUFFER_LEVEL (0x12)
Name Bit Access Description Reset
Buffer level 31:0 RO Indicates the number of data packets present in the buffer. 0x0